Rajul Bansal

Orcid: 0000-0001-7794-8025

According to our database1, Rajul Bansal authored at least 7 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Closely-Coupled Lifting Hardware for Efficient DWT Computation in an SoC.
J. Signal Process. Syst., 2020

PRESENT Crypto-core as Closely-coupled Coprocessor for Efficient Embedded SoCs.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019
Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2017
Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design.
Microprocess. Microsystems, 2017

A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2011
High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2005
<i>SenSlide</i>: a sensor network based landslide prediction aystem.
Proceedings of the 3rd International Conference on Embedded Networked Sensor Systems, 2005


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