Rama Muni Reddy Yanamala

According to our database, Rama Muni Reddy Yanamala authored at least 20 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

FPGA-Powered Solar Photovoltaic Module Defect Classification: Patch-Wise Reusable Convolutional Neural Network Intellectual Properties for High-Speed Edge Processing.

Ghanashyam Vinod, Rama Muni Reddy Yanamala, Rayappa David Amar Raj, T. Subeesh, V. Anandkumar, Rouzbeh Nazari, Manasa V, Archana Pallakonda

J. Comput. Inf. Sci. Eng., 2026

Elevating efficiency: Field-Programmable Gate Array Powered Acceleration of MobileNet V1 with patchwise innovation, double buffering, and Singular Value Decomposition Optimization.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam, Rayappa David Amar Raj

Eng. Appl. Artif. Intell., 2026

Formalized dual-stream hybrid convolutional neural network for efficient multi-scale tampering detection via feature-driven fusion.

Archana Pallakonda, Rama Muni Reddy Yanamala, Enku Sai Mohith, Rayappa David Amar Raj

Eng. Appl. Artif. Intell., 2026

Hierarchical mobile-dense convolutional architecture for tampered image detection using focal optimization with quantized edge TPU deployment.

Badam Shanmukha Venkata Vinayak, Rama Muni Reddy Yanamala, Rayappa David Amar Raj, Archana Pallakonda

Comput. Electr. Eng., 2026

2025

FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

J. Supercomput., February, 2025

TL-Efficient-SE: A Transfer Learning-Based Attention-Enhanced Model for Fingerprint Liveness Detection Across Multi-Sensor Spoof Attacks.

Archana Pallakonda, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, Christian Napoli, Cristian Randieri

Mach. Learn. Knowl. Extr., 2025

Lightweight spatial attention pyramid network-based image forgery detection optimized for real-time edge TPU deployment.

Baby Sree Gangarapu, Rama Muni Reddy Yanamala, Archana Pallakonda, Hindupur Raghavender Vardhan, Rayappa David Amar Raj

Comput. Electr. Eng., 2025

YOLOv8n-GBE: A Hybrid YOLOv8n Model With Ghost Convolutions and BiFPN-ECA Attention for Solar PV Defect Localization.

Likitha Reddy Yeddula, Archana Pallakonda, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, K. Krishna Prakasha, Mallempati Sunil Kumar

IEEE Access, 2025

A Holistic Framework for Cyber Attack Detection, Classification, and Security Enhancement of DNP3 Protocol in Smart Grids.

Jyothsna Vaasudevan, Harish Manukonda, Archana Pallakonda, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, Rouzbeh Nazari, K. Krishna Prakasha

IEEE Access, 2025

A Unified Cybersecurity Framework for Smart Grids Against Data Integrity Attacks Using Ensemble Learning and Hybrid Encryption.

Archana Pallakonda, K. Ravishanmugam, Rayappa David Amar Raj, Sharvesh Sivagnanam, Rama Muni Reddy Yanamala, K. Krishna Prakasha

IEEE Access, 2025

Secure and Resilient Cyberattack Detection in ICS Networks: Hybrid Encryption, Protocol Hardening, and Threat Hunting on ELECTRA Modbus Traffic.

Archana Pallakonda, S. Sanjay Kumar, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, K. Krishna Prakasha

IEEE Access, 2025

Smart Grid Intrusion Detection for IEC 60870-5-104 With Feature Optimization, Privacy Protection, and Honeypot-Firewall Integration.

Pedamallu Sai Mrudula, Rayappa David Amar Raj, Archana Pallakonda, Rama Muni Reddy Yanamala, K. Krishna Prakasha, V. Anand Kumar

IEEE Access, 2025

FPGA-Accelerated Sparse Subset Segmentation Using ADMM for High-Resolution Imagery.

Rupali Karthikeyan, Deep Amit Lodaya, Rama Muni Reddy Yanamala, Rayappa David Amar Raj, K. Krishna Prakasha, T. Subeesh, V. Anandkumar, Archana Pallakonda

IEEE Access, 2025

Lightweight End-to-End Patch-Based Self-Attention Network for Robust Image Forgery Detection.

Police Aryan, Rama Muni Reddy Yanamala, Archana Pallakonda, Rayappa David Amar Raj, K. Krishna Prakasha

IEEE Access, 2025

A Neural Framework For Handwritten Calendar Parsing and Semantic Content Categorization.

Antoni Gagliard, Rayappa David Amar Raj, Rama Muni Reddy Yanamala

Proceedings of the 10th International Conference of Yearly Reports on Informatics, 2025

2024

High-Speed Power Allocation in NOMA System Using FPGA-Based DNN.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

J. Circuits Syst. Comput., September, 2024

Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

Int. J. Circuit Theory Appl., September, 2024

2023

A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

Des. Autom. Embed. Syst., September, 2023

Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU.

Sujay Kumar Mandal, Muralidhar Pullakandam, Rama Muni Reddy Yanamala

Proceedings of the 14th International Conference on Computing Communication and Networking Technologies, 2023

2022

An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device.

Rama Muni Reddy Yanamala, Muralidhar Pullakandam

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022