# Ramachandra Achar

According to our database

Collaborative distances:

^{1}, Ramachandra Achar authored at least 48 papers between 1995 and 2023.Collaborative distances:

## Awards

## IEEE Fellow

IEEE Fellow 2013, "For contributions to interconnect and signal integrity analysis in high-speed designs".

## Timeline

#### Legend:

Book In proceedings Article PhD thesis Dataset Other## Links

#### On csauthors.net:

## Bibliography

2023

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

2022

DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs.

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation.

IEEE Access, 2022

Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters.

IEEE Access, 2022

2021

GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

DPCrypto: Acceleration of Post-quantum Cryptographic Algorithms using Dot-Product Instruction on GPUs.

IACR Cryptol. ePrint Arch., 2021

2020

An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications.

Microprocess. Microsystems, 2020

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers.

IEEE Access, 2019

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018

IEEE Trans. Very Large Scale Integr. Syst., 2018

IEEE Trans. Very Large Scale Integr. Syst., 2018

2017

Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits.

IEEE Trans. Very Large Scale Integr. Syst., 2017

2014

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

Efficient parallel scheduler for circuit simulation exploiting binary link formulations.

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012

Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR).

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels.

IEEE Trans. Very Large Scale Integr. Syst., 2009

A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels.

IEEE Trans. Very Large Scale Integr. Syst., 2007

Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits.

INFORMS J. Comput., 2006

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.

IEEE Trans. Very Large Scale Integr. Syst., 2005

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

On passivity enforcement for macromodels of S-parameter based tabulated subnetworks.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters.

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques.

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast sensitivity analysis of transmission line networks.

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Passive closed-form time-domain macromodels for on-chip distributed RC interconnects.

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

Proc. IEEE, 2001

Proc. IEEE, 2001

A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations.

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Proceedings of the 37th Conference on Design Automation, 2000

1999

Proceedings of the VLSI Handbook., 1999

Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques.

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1996

An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data.

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Addressing high frequency effects in VLSI interconnects with full wave model and CFH.

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995