Ramachandra Achar

According to our database1, Ramachandra Achar authored at least 35 papers between 1995 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2013, "For contributions to interconnect and signal integrity analysis in high-speed designs".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers.
IEEE Access, 2019

A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018
Fast Analysis of Time Interval Error in Current-Mode Drivers.
IEEE Trans. VLSI Syst., 2018

Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation.
IEEE Trans. VLSI Syst., 2018

2017
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits.
IEEE Trans. VLSI Syst., 2017

2014
Addressing Partitioning Issues in Parallel Circuit Simulation.
IEEE Trans. VLSI Syst., 2014

2012
Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

2011
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR).
IEEE Trans. VLSI Syst., 2011

2010
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

2009
Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels.
IEEE Trans. VLSI Syst., 2009

A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

2008
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

2007
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels.
IEEE Trans. VLSI Syst., 2007

Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Sparse and passive reduction of massively coupled large multiport interconnects.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits.
INFORMS Journal on Computing, 2006

Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.
IEEE Trans. VLSI Syst., 2005

Passivity verification in delay-based macromodels of electrical interconnects.
IEEE Trans. on Circuits and Systems, 2005

Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

On passivity enforcement for macromodels of S-parameter based tabulated subnetworks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Fast sensitivity analysis of transmission line networks.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Passive macromodeling of subnetworks characterized by measured data.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2000
Simulation of high-speed distributed interconnects using Krylov-space techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Passive model order reduction of multiport distributed interconnects.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Interconnect Modeling and Simulation.
Proceedings of the VLSI Handbook., 1999

Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Efficient simulation of on-chip RF components using model-reduction techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Full-wave analysis of high-speed interconnects using complex frequency hopping.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

1996
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Addressing high frequency effects in VLSI interconnects with full wave model and CFH.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995


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