Ramana Ranganatham

According to our database, Ramana Ranganatham authored at least 3 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A Sub-μA LDO With Analog Adaptive Enhancements for Scalable PSRR, Load Range, and Bandwidth Extension.

Daniel Zeznick, Ramana Ranganatham, Jacob O'Donnell, Chirag Adiga, Will B. Wright, Tejasvi Das

IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026

2025

An All Analog Temporal Power-supply Trojan to Subvert ECG Biometric Authentication.

Ramana Ranganatham, Roberto Ramos-Brito, Michael Zuzak, Tejasvi Das

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024

An Analog Payload Trojan via Power-Supply Harmonic Coupling in Front-End Circuits.

Ramana Ranganatham, Tejasvi Das

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024