Michael Zuzak

Orcid: 0000-0003-0356-9393

According to our database1, Michael Zuzak authored at least 24 papers between 2018 and 2024.

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Bibliography

2024
Complementing Vehicle Trajectories Using Two Camera Viewpoints.
Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023
Security-Aware Resource Binding to Enhance Logic Obfuscation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Fusion is Not Enough: Single-Modal Attacks to Compromise Fusion Models in Autonomous Driving.
CoRR, 2023

Low Overhead System-Level Obfuscation through Hardware Resource Sharing.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Exploiting Logic Locking for a Neural Trojan Attack on Machine Learning Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Designing Effective Logic Obfuscation: Exploring Beyond Gate-Level Boundaries.
PhD thesis, 2022

Evaluating the Security of Logic-Locked Probabilistic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Black-Box Sensitization Attack on SAT-Hard Instances in Logic Obfuscation.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

A Combined Logical and Physical Attack on Logic Obfuscation.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Survey on Side-Channel-based Reverse Engineering Attacks on Deep Neural Networks.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Trace Logic Locking: Improving the Parametric Space of Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Robust and Attack Resilient Logic Locking with a High Application-Level Impact.
ACM J. Emerg. Technol. Comput. Syst., 2021

Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design.
IACR Cryptol. ePrint Arch., 2021

A Resource Binding Approach to Logic Obfuscation.
IACR Cryptol. ePrint Arch., 2021

Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Keynote: A Disquisition on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Nested MIMD-SIMD Parallelization for Heterogeneous Microprocessors.
ACM Trans. Archit. Code Optim., 2020

Strong Anti-SAT: Secure and Effective Logic Locking.
IACR Cryptol. ePrint Arch., 2020

A Survey on Neural Trojans.
IACR Cryptol. ePrint Arch., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

StatSAT: A Boolean Satisfiability based Attack on Logic-Locked Probabilistic Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Memory Locking: An Automated Approach to Processor Design Obfuscation.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation.
Proceedings of the International Symposium on Memory Systems, 2018


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