Rangababu Peesapati

Orcid: 0000-0003-2645-7634

Affiliations:
  • National Institute of Technology, Meghalaya, India


According to our database1, Rangababu Peesapati authored at least 36 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
FPGA-Based Hardware Accelerator for Matrix Inversion.
SN Comput. Sci., March, 2023

Design and Development of Artificial Intelligence-Enabled IoT Framework for Satellite-Based Navigation Services.
IEEE Trans. Geosci. Remote. Sens., 2023

2022
Design and Implementation of Gray-Coded Bit-Plane Based Reconfigurable Motion Estimation Architecture Using Binary Content Addressable Memory for Video Encoder.
IEEE Trans. Consumer Electron., 2022

2021
A Novel Modified Control Scheme in Grid-Tied Photovoltaic System for Power Quality Enhancement.
IEEE Trans. Ind. Electron., 2021

Design and Implementation of an Efficient Multi-Pattern Motion Estimation Search Algorithm for HEVC/H.265.
IEEE Trans. Consumer Electron., 2021

An Improved Adaptive Control Strategy in Grid-Tied PV System With Active Power Filter for Power Quality Enhancement.
IEEE Syst. J., 2021

A directional and scalable streaming deblocking filter hardware architecture for HEVC decoder.
Microprocess. Microsystems, 2021

A hybrid hardware oriented motion estimation algorithm for HEVC/H.265.
J. Real Time Image Process., 2021

Optimal spectrum and power allocation using evolutionary algorithms for cognitive radio networks.
Internet Technol. Lett., 2021

System on chip implementation of floating point matrix inversion using modified Gram-Schmidt based QR decomposition on PYNQ FPGA.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
Scalable Wavefront Parallel Streaming Deblocking Filter Hardware for HEVC Decoder.
IEEE Trans. Consumer Electron., 2020

Attenuation Factor approach to minimize the correlation effect in Soft Output Viterbi Algorithm.
Phys. Commun., 2020

A Motion Estimation Search Algorithm and its Hardware Implementation for HEVC/H.265.
Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020

2019
Hardware Implementation of Video Processing Device using Residue Number System.
Proceedings of the 42nd International Conference on Telecommunications and Signal Processing, 2019

An Adaptive Current Control Technique in Grid-tied PV System with Active Power Filter for Power Quality Improvement.
Proceedings of the TENCON 2019, 2019

A Pre-filtering based Current Control Strategy in Grid-tied Photovoltaic Systems with Active Power Filter for Harmonic Mitigation.
Proceedings of the TENCON 2019, 2019

Programmable Auxiliary Co-Processing Unit for H.264 Decoder.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

A Hybrid Motion Estimation Search Algorithm for HEVC/H.265.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

A Stress Sensitive CMOS Operational Amplifier Based Pressure Sensor with Varying Input and Gain.
Proceedings of the 9th IEEE International Conference on System Engineering and Technology, 2019

2018
Design and Implementation of Efficient Streaming Deblocking and SAO Filter for HEVC Decoder.
IEEE Trans. Consumer Electron., 2018

FPGA-based implementation for improved control scheme of grid-connected PV system with 3-phase 3-level NPC-VSI.
Int. J. Circuit Theory Appl., 2018

Sensitivity Enhancement of Current Mirror Readout Circuit Based Piezoresistive Pressure Transducer Using Differential Amplifier.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2017
An Implementation of Hybrid Control Strategy for Distributed Generation System Interface Using Xilinx System Generator.
IEEE Trans. Ind. Informatics, 2017

Design of streaming deblocking filter for HEVC decoder.
IEEE Trans. Consumer Electron., 2017

Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015
Field programmable gate array implementation of spectrum allocation technique for cognitive radio networks.
Comput. Electr. Eng., 2015

2014
Comparative study of system on chip based solution for floating and fixed point differential evolution algorithm.
Swarm Evol. Comput., 2014

FPGA-based embedded platform for fiber optic gyroscope signal denoising.
Int. J. Circuit Theory Appl., 2014

Corrigendum to "FPGA based Embedded platform for Fiber Optic Gyroscope signal denoising", doi: 10.1002/cta.1883.
Int. J. Circuit Theory Appl., 2014

2013
Field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network.
IET Comput. Digit. Tech., 2013

Design and implementation of a realtime co-processor for denoising Fiber Optic Gyroscope signal.
Digit. Signal Process., 2013

2012
SoC based floating point implementation of differential evolution algorithm using FPGA.
Des. Autom. Embed. Syst., 2012

2011
Differential Evolution Algorithm for Motion Estimation.
Proceedings of the Multi-disciplinary Trends in Artificial Intelligence, 2011

System on Chip Implementation of Adaptive Moving Average Based Multiple-Model Kalman Filter for Denoising Fiber Optic Gyroscope Signal.
Proceedings of the International Symposium on Electronic System Design, 2011

2009
Reliable High Speed Data Acquisition System Using FPGA.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009


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