Shashi Kumar

According to our database1, Shashi Kumar authored at least 82 papers between 1989 and 2021.

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Bibliography

2021
Deep learning-based models for temporal satellite data processing: Classification of paddy transplanted fields.
Ecol. Informatics, 2021

SRIB Submission to Interspeech 2021 DiCOVA Challenge.
CoRR, 2021

2020
Snow Density Retrieval Using Hybrid Polarimetric RISAT-1 Datasets.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2020

Estimation of Soil Moisture Applying Modified Dubois Model to Sentinel-1; A Regional Study from Central India.
Remote. Sens., 2020

Investigating the Retention of Solar Wind Implanted Helium-3 on the Moon from the Analysis of Multi-Wavelength Remote Sensing Data.
Remote. Sens., 2020

Rooftop Photovoltaic Energy Production Management in India Using Earth-Observation Data and Modeling Techniques.
Remote. Sens., 2020

Spaceborne Multifrequency PolInSAR-Based Inversion Modelling for Forest Height Retrieval.
Remote. Sens., 2020

A Hybrid Distributed Model for Learning Representation of Short Texts with Attribute Labels.
Proceedings of the CoDS-COMAD 2020: 7th ACM IKDD CoDS and 25th COMAD, 2020

2019
Evaluation of Hybrid Polarimetric Decomposition Techniques for Forest Biomass Estimation.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019

Polarimetric Calibration of RISAT-1 Compact-Pol Data.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019

PolSAR-Decomposition-Based Extended Water Cloud Modeling for Forest Aboveground Biomass Estimation.
Remote. Sens., 2019

Far-Field Speech Enhancement Using Heteroscedastic Autoencoder for Improved Speech Recognition.
Proceedings of the Interspeech 2019, 2019

X-Band Polarimetric Sar Copolar Phase Difference for Fresh Snow Depth Estimation in the Northwestern Himalayan Watershed.
Proceedings of the 2019 IEEE International Geoscience and Remote Sensing Symposium, 2019

A Stress Sensitive CMOS Operational Amplifier Based Pressure Sensor with Varying Input and Gain.
Proceedings of the 9th IEEE International Conference on System Engineering and Technology, 2019

Joint Distribution Learning in the Framework of Variational Autoencoders for Far-Field Speech Enhancement.
Proceedings of the IEEE Automatic Speech Recognition and Understanding Workshop, 2019

2018
Potential of Space-Borne PolInSAR for Forest Canopy Height Estimation Over India - A Case Study Using Fully Polarimetric L-, C-, and X-Band SAR Data.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2018

Minimization of the ambiguity of merging of urban builtup and fallow land features by generating 'C2' covariance matrix using spaceborne bistatic dual Pol SAR data.
Proceedings of the 2018 4th International Conference on Recent Advances in Information Technology (RAIT), 2018

Remote Compositional Pyroxene Estimates in the Reiner Gamma Formation Using Feature-Oriented Pca: New Insights Into Lunar Swirls.
Proceedings of the 2018 IEEE International Geoscience and Remote Sensing Symposium, 2018

2017
Spaceborne PolSAR Tomography for Forest Height Retrieval.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2017

2016
PCB Defect Classification Using Logical Combination of Segmented Copper and Non-copper Part.
Proceedings of International Conference on Computer Vision and Image Processing, 2016

2015
On Optimizing Human-Machine Task Assignments.
CoRR, 2015

2014
Optimized Power Efficient Routing in Ad-hoc Networks.
Int. J. Next Gener. Comput., 2014

2013
An Efficient Router Architecture and Its FPGA Prototyping to Support Junction Based Routing in NoC Platforms.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
A note on the solution of singular boundary value problems arising in engineering and applied sciences: Use of OHAM.
Comput. Chem. Eng., 2012

Junction based routing: a scalable technique to support source routing in large NoC platforms.
Proceedings of the Fifth International Workshop on Network on Chip Architectures, 2012

2011
Network-on-chip architectures and design methodologies.
Microprocess. Microsystems, 2011

An Abstraction to Support Design of Deadlock-free Routing Algorithms for Large and Hierarchical NoCs.
Proceedings of the 11th IEEE International Conference on Computer and Information Technology, 2011

Application-Specific Routing Algorithms for Low Power Network on Chip Design.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Multi-level Routing Scheme and Router Architecture to Support Hierarchical Routing in Large Network on Chip Platforms.
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010

An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Application Specific Routing Algorithms for Networks on Chip.
IEEE Trans. Parallel Distributed Syst., 2009

Bandwidth-aware routing algorithms for networks-on-chip platforms.
IET Comput. Digit. Tech., 2009

Enabling web services for Classification of Satellite Image.
Proceedings of the 2009 International Conference on Semantic Web & Web Services, 2009

HiRA: A methodology for deadlock free routing in hierarchical networks on chip.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Swarm Intelligence Inspired Classifiers in Comparison with Fuzzy and Rough Classifiers: A Remote Sensing Approach.
Proceedings of the Contemporary Computing - Second International Conference, 2009

Distance Constrained Mapping to Support NoC Platforms Based on Source Routing.
Proceedings of the Euro-Par 2009, 2009

2008
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions.
J. Syst. Archit., 2008

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols.
IET Comput. Digit. Tech., 2008

Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Networks-on-Chip: Emerging Research Topics and Novel Ideas.
VLSI Design, 2007

Corrections to Chen and Chiu's Fault Tolerant Routing Algorithm for Mesh Networks.
J. Inf. Sci. Eng., 2007

Prediction of flow stress for carbon steels using recurrent self-organizing neuro fuzzy networks.
Expert Syst. Appl., 2007

Letter to the Editor.
Comput. Chem. Eng., 2007

Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Solving Part-Type Selection and Operation Allocation Problems in an FMS: An Approach Using Constraints-Based Fast Simulated Annealing Algorithm.
IEEE Trans. Syst. Man Cybern. Part A, 2006

A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Off-Line Testing of Delay Faults in NoC Interconnects.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A methodology for design of application specific deadlock-free routing algorithms for NoC systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Slack-time aware routing in NoC systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing.
Des. Autom. Embed. Syst., 2003

Extending Platform-Based Design to Network on Chip Systems.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Modelling and Evaluation of a Network on Chip Architecture Using SDL.
Proceedings of the SDL 2003: System Design, 2003

Algorithms and Tools for Network on Chip Based System Design.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

On Packet Switched Networks for On-Chip Communication.
Proceedings of the Networks on Chip, 2003

2002
Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

A Network on Chip Architecture and Design Methodology.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

2000
A Metamodel for Studying Concepts in Electronic System Design.
IEEE Des. Test Comput., 2000

Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Evaluation of Various Routing Architectures for Multi-FPGA Boards.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.
Proceedings of the Field-Programmable Logic and Applications, 2000

1999
Globally asynchronous locally synchronous architecture for large high-performance ASICs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems.
Proceedings of the 1999 Design, 1999

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997
Multiobjective Search Based Algorithms for Circuit Partitioning Problem for Acceleration of Logic Simulation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Novel Reconfigurable Co-Processor Architecture.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996
Iterative Deepening Multiobjective A.
Inf. Process. Lett., 1996

1995
An HOL based framework for design of correct high level synthesizers.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Circuit partitioning with partial order for mixed simulation emulation environment.
Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

1993
High Level Design Experiences with IDEAS.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
A heuristic search strategy for optimization of trade-off cost measures.
Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991

1989
Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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