Ravi Tej Uppu

According to our database1, Ravi Tej Uppu authored at least 2 papers between 2013 and 2014.

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Bibliography

2014
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013


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