Ilia Polian

Orcid: 0000-0002-6563-2725

Affiliations:
  • Stuttgart University, Germany
  • University of Passau, Germany (former)


According to our database1, Ilia Polian authored at least 212 papers between 1999 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Memristive True Random Number Generator for Security Applications.
Sensors, August, 2024

Synergistic Dynamical Decoupling and Circuit Design for Enhanced Algorithm Performance on Near-Term Quantum Devices.
Entropy, July, 2024

Locking-Enabled Security Analysis of Cryptographic Circuits.
Cryptogr., March, 2024

Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties.
CoRR, 2024

Scenario-based Test Content Optimization: Scan Test vs. System-Level Test.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Refinement and Empirical Side-Channel Analysis of Inner Product Masking with Robust Error Detection.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024

Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties.
Proceedings of the IEEE European Test Symposium, 2024

Optimizing System-Level Test Program Generation via Genetic Programming.
Proceedings of the IEEE European Test Symposium, 2024

Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design.
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

Enabling Power Side-Channel Attack Simulation on Mixed-Signal Neural Network Accelerators.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2024

Attacking a Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
On Side-Channel Analysis of Memristive Cryptographic Circuits.
IEEE Trans. Inf. Forensics Secur., 2023

Benchmarking the performance of portfolio optimization with QAOA.
Quantum Inf. Process., 2023

Power-balanced Memristive Cryptographic Implementation Against Side Channel Attacks.
CoRR, 2023

Optimal Qubit Reuse for Near-Term Quantum Computers.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Overview of Memristive Cryptography.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Design Rationale for Symbiotically Secure Key Management Systems in IoT and Beyond.
Proceedings of the 9th International Conference on Information Systems Security and Privacy, 2023

Exploring Gate-Diversity Enabled by Reconfigurable Memristive Technology.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

LEDA: Locking Enabled Differential Analysis of Cryptographic Circuits.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Automating Greybox System-Level Test Generation.
Proceedings of the IEEE European Test Symposium, 2023

Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing.
Proceedings of the IEEE European Test Symposium, 2023


Stochastic Computing as a Defence Against Adversarial Attacks.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

A Modular Open-Source Cryptographic Co-Processor for Internet of Things.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Side-channel Attacks on Memristive Circuits Under External Disturbances.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Physics inspired compact modelling of BiFeO$_3$ based memristors for hardware security applications.
CoRR, 2022

Calibration-Aware Transpilation for Variational Quantum Optimization.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2022

Wavelet Transform Assisted Neural Networks for Human Activity Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Human vs. Automatic Detection of Deepfake Videos Over Noisy Channels.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2022

On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks.
Proceedings of the IEEE European Test Symposium, 2022

Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization.
Proceedings of the IEEE European Test Symposium, 2022

Stochastic Computing Architectures for Lightweight LSTM Neural Networks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022


On the Limitations of Logic Locking the Approximate Circuits.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021
Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., 2021

IPM-RED: combining higher-order masking with robust error detection.
J. Cryptogr. Eng., 2021

Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications.
IEEE Des. Test, 2021

Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning.
CAAI Trans. Intell. Technol., 2021

Special Session: Noisy Intermediate-Scale Quantum (NISQ) Computers - How They Work, How They Fail, How to Test Them?
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Special Session: Machine Learning for Semiconductor Test and Reliability.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Error Analysis of the Variational Quantum Eigensolver Algorithm.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

System-Level Test: State of the Art and Challenges.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Optimal Mapping for Near-Term Quantum Architectures based on Rydberg Atoms.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

ArsoNISQ: Analyzing Quantum Algorithms on Near-Term Architectures.
Proceedings of the 26th IEEE European Test Symposium, 2021


Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021


On resilience of security-oriented error detecting architectures against power attacks: a theoretical analysis.
Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020
Error control scheme for malicious and natural faults in cryptographic modules.
J. Cryptogr. Eng., 2020

Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks.
Proceedings of the Media Watermarking, 2020

Retraining and Regularization to Optimize Neural Networks for Stochastic Computing.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

An Open-Source Area-Optimized ECEG Cryptosystem in Hardware.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Hardware-based Fast Real-time Image Classification with Stochastic Computing.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Side Channel Attacks vs Approximate Computing.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Exploring the Mysteries of System-Level Test.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Improving Testability and Reliability of Advanced SRAM Architectures.
IEEE Trans. Emerg. Top. Comput., 2019

Hardware-oriented security.
it Inf. Technol., 2019

Toward Error-Correcting Architectures for Cryptographic Circuits Based on Rabii-Keren Codes.
IEEE Embed. Syst. Lett., 2019

Secure Composition for Hardware Systems (Dagstuhl Seminar 19301).
Dagstuhl Reports, 2019

Fault Sensitivity Analysis of Lattice-Based Post-Quantum Cryptographic Components.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives.
Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019

Fault Attacks on Cryptographic Circuits.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Electroforming-free Memristors for Hardware Security Primitives.
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

On the Limits of Stochastic Computing.
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019

Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019

Security in Autonomous Systems.
Proceedings of the 24th IEEE European Test Symposium, 2019

On the maximum function in stochastic computing.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
S-box-based random number generation for stochastic computing.
Microprocess. Microsystems, 2018

Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design.
ACM J. Emerg. Technol. Comput. Syst., 2018

Test and Reliability Challenges for Approximate Circuitry.
IEEE Embed. Syst. Lett., 2018

Quantum era challenges for classical computers.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Security: the dark side of approximate computing?
Proceedings of the International Conference on Computer-Aided Design, 2018

Hardware-oriented Security in a Computer Science Curriculum.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

Security-oriented Code-based Architectures for Mitigating Fault Attacks.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Detection and Correction of Malicious and Natural Faults in Cryptographic Modules.
Proceedings of the PROOFS 2018, 2018

2017
Introduction to hardware-oriented security for MPSoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Towards mixed structural-functional models for algebraic fault attacks on ciphers.
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

AutoFault: Towards Automatic Construction of Algebraic Fault Attacks.
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017

Counteracting malicious faults in cryptographic circuits.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Building a Better Random Number Generator for Stochastic Computing.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Sensitized path PUF: A lightweight embedded physical unclonable function.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Analyzing the effects of peripheral circuit aging of embedded SRAM architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Securing the hardware of cyber-physical systems.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization.
IEEE Trans. Computers, 2016

Hardware Security (Dagstuhl Seminar 16202).
Dagstuhl Reports, 2016

Detection Performance of MIMO Unique Word OFDM.
Proceedings of the WSA 2016, 2016

Memory error resilient detection for massive MIMO systems.
Proceedings of the 24th European Signal Processing Conference, 2016

Failure mechanisms and test methods for the SRAM TVC write-assist technique.
Proceedings of the 21th IEEE European Test Symposium, 2016

Improving SRAM test quality by leveraging self-timed circuits.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

On Optimal Power-Aware Path Sensitization.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Formal Vulnerability Analysis of Security Components.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Fully Fault-Tolerant Representation of Quantum Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Fault-based attacks on the Bel-T block cipher family.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Design automation challenges for scalable quantum architectures.
Proceedings of the 52nd Annual Design Automation Conference, 2015

On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Hardware security and test: Friends or enemies?
it Inf. Technol., 2014

Guest Editorial.
IET Comput. Digit. Tech., 2014

Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis.
IACR Cryptol. ePrint Arch., 2014

Parametric Trojans for Fault-Injection Attacks on Cryptographic Hardware.
IACR Cryptol. ePrint Arch., 2014

Reliability analysis of MIMO channel preprocessing by fault injection.
Proceedings of the 2014 IEEE International Conference on Wireless for Space and Extreme Environments, 2014

Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

SAT-Based Test Pattern Generation with Improved Dynamic Compaction.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Cross-Level Validation of Topological Quantum Circuits.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Variation-aware deterministic ATPG.
Proceedings of the 19th IEEE European Test Symposium, 2014

Detection conditions for errors in self-adaptive better-than-worst-case designs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Protecting cryptographic hardware against malicious attacks by nonlinear robust codes.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Software-based Pauli tracking in fault-tolerant quantum circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Technische Informatik in der universitären Lehre: Bestandsaufnahme, Herausforderungen, Perspektiven.
Proceedings of the Aspekte der Technischen Informatik, 2014

2013
Multi-Stage Fault Attacks on Block Ciphers.
IACR Cryptol. ePrint Arch., 2013

SAT-Based Analysis of Sensitizable Paths.
IEEE Des. Test, 2013

Special session 12A: Hot topic counterfeit IC identification: How can test help?
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.
Proceedings of the 14th Latin American Test Workshop, 2013

Approximate simulation of circuits with probabilistic behavior.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Fault-based attacks on cryptographic hardware.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.
Proceedings of the Design, Automation and Test in Europe, 2013

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator.
Proceedings of the 22nd Asian Test Symposium, 2013

Provably optimal test cube generation using quantified boolean formula solving.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
An Algebraic Fault Attack on the LED Block Cipher.
IACR Cryptol. ePrint Arch., 2012

SAT-ATPG using preferences for improved detection of complex defect mechanisms.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Synthesis of topological quantum circuits.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Functional test of small-delay faults using SAT and Craig interpolation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Cross-level protection of circuits against faults and malicious attacks.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Small-delay-fault ATPG with waveform accuracy.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

On the quality of test vectors for post-silicon characterization.
Proceedings of the 17th IEEE European Test Symposium, 2012

Multi-conditional SAT-ATPG for power-droop testing.
Proceedings of the 17th IEEE European Test Symposium, 2012

#SAT-based vulnerability analysis of security components - A case study.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

On the optimality of K longest path generation algorithm under memory constraints.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A Fault Attack on the LED Block Cipher.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Variation-Aware Fault Grading.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Detection and diagnosis of faulty quantum circuits.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Modeling and Mitigating Transient Errors in Logic Circuits.
IEEE Trans. Dependable Secur. Comput., 2011

Selective Hardening: Toward Cost-Effective Error Tolerance.
IEEE Des. Test Comput., 2011

Variation-aware fault modeling.
Sci. China Inf. Sci., 2011

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Estimation of component criticality in early design steps.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Towards Variation-Aware Test Methods.
Proceedings of the 16th European Test Symposium, 2011

Tomographic Testing and Validation of Probabilistic Circuits.
Proceedings of the 16th European Test Symposium, 2011

SAT-based analysis of sensitisable paths.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Adaptive voltage over-scaling for resilient applications.
Proceedings of the Design, Automation and Test in Europe, 2011

Efficient SAT-Based Search for Longest Sensitisable Paths.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Power Supply Noise: Causes, Effects, and Testing.
J. Low Power Electron., 2010

Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).
it Inf. Technol., 2010

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis.
Int. J. Parallel Program., 2010

Special session 4B: Panel low-power test and noise-aware test: Foes or friends?
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Advanced modeling of faults in Reversible circuits.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

2009
SUPERB: Simulator utilizing parallel evaluation of resistive bridges.
ACM Trans. Design Autom. Electr. Syst., 2009

An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

ATPG-based grading of strong fault-secureness.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Reducing temperature variability by routing heat pipes.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Analysis and optimization of fault-tolerant embedded systems with hardened processors.
Proceedings of the Design, Automation and Test in Europe, 2009

Dynamic Compaction in SAT-Based ATPG.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Automatic Test Pattern Generation for Interconnect Open Defects.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
Proceedings of the 2008 IEEE International Test Conference, 2008

Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Selective Hardening in Early Design Steps.
Proceedings of the 13th European Test Symposium, 2008

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects.
Proceedings of the 13th European Test Symposium, 2008

A study of cognitive resilience in a JPEG compressor.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

On Reducing Circuit Malfunctions Caused by Soft Errors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Selective Hardening of NanoPLA Circuits.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Resistive Bridging Fault Simulation of Industrial Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Functional Constraints vs. Test Compression in Scan-Based Delay Testing.
J. Electron. Test., 2007

Power Droop Testing.
IEEE Des. Test Comput., 2007

Electromechanical Reliability Testing of Three-Axial Silicon Force Sensors
CoRR, 2007

An Analysis Framework for Transient-Error Tolerance.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Identification of Critical Errors in Imaging Applications.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Simulating Open-Via Defects.
Proceedings of the 16th Asian Test Symposium, 2007

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges.
Proceedings of the 16th Asian Test Symposium, 2007

2006
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Simulating Resistive-Bridging and Stuck-At Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it Inf. Technol., 2006

Automatic Test Pattern Generation for Resistive Bridging Faults.
J. Electron. Test., 2006

A Definition and Classification of Timing Anomalies.
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006

An Improved Technique for Reducing False Alarms Due to Soft Errors.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Low-Cost Hardening of Image Processing Applications Against Soft Errors.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency.
Proceedings of the 15th Asian Test Symposium, 2006

Delta-IDDQ Testing of Resistive Short Defects.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications).
it Inf. Technol., 2005

Modeling Feedback Bridging Faults with Non-Zero Resistance.
J. Electron. Test., 2005

Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Transient fault characterization in dynamic noisy environments.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Evolutionary Optimization in Code-Based Test Compression.
Proceedings of the 2005 Design, 2005

A Family of Logical Fault Models for Reversible Circuits.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Scalable Delay Fault BIST for Use with Low-Cost ATE.
J. Electron. Test., 2004

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Testing for Missing-Gate Faults in Reversible Circuits.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Pattern-based verification of connections to intellectual property cores.
Integr., 2003

Multiple Scan Chain Design for Two-Pattern Testing.
J. Electron. Test., 2003

Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting.
J. Electron. Test., 2003

Reducing ATE Cost in System-on-Chip Test.
Proceedings of the IFIP VLSI-SoC 2003, 2003

The Case for 2-POF.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

On non-standard fault models for logic digital circuits.
Proceedings of the Ausgezeichnete Informatikdissertationen 2003, 2003

Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST.
Proceedings of the 2003 Design, 2003

2002
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Sequential n -Detection Criteria: Keep It Simple.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Stop & Go BIST.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Efficient Pattern-Based Verification of Connections to IP Cores .
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
A scalable BIST architecture for delay faults.
Proceedings of the 4th European Test Workshop, 1999


  Loading...