Ilia Polian
Orcid: 0000-0002-6563-2725Affiliations:
- Stuttgart University, Germany
- University of Passau, Germany (former)
According to our database1,
Ilia Polian
authored at least 203 papers
between 1999 and 2024.
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Bibliography
2024
Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties.
CoRR, 2024
2023
IEEE Trans. Inf. Forensics Secur., 2023
Quantum Inf. Process., 2023
CoRR, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 9th International Conference on Information Systems Security and Privacy, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Physics inspired compact modelling of BiFeO$_3$ based memristors for hardware security applications.
CoRR, 2022
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Conference on Multimedia and Expo, 2022
On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks.
Proceedings of the IEEE European Test Symposium, 2022
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
2021
Introduction to the Special Issue on Emerging Challenges and Solutions in Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., 2021
J. Cryptogr. Eng., 2021
IEEE Des. Test, 2021
Protecting artificial intelligence IPs: a survey of watermarking and fingerprinting for machine learning.
CAAI Trans. Intell. Technol., 2021
Special Session: Noisy Intermediate-Scale Quantum (NISQ) Computers - How They Work, How They Fail, How to Test Them?
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
On resilience of security-oriented error detecting architectures against power attacks: a theoretical analysis.
Proceedings of the CF '21: Computing Frontiers Conference, 2021
2020
J. Cryptogr. Eng., 2020
Detection of Malicious Spatial-Domain Steganography over Noisy Channels Using Convolutional Neural Networks.
Proceedings of the Media Watermarking, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
Toward Error-Correcting Architectures for Cryptographic Circuits Based on Rabii-Keren Codes.
IEEE Embed. Syst. Lett., 2019
Dagstuhl Reports, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
A comment on information leakage from robust code-based checkers detecting fault attacks on cryptographic primitives.
Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 4th IEEE International Verification and Security Workshop, 2019
Proceedings of the 2019 IEEE International Conference on Rebooting Computing, 2019
Hardware-Oriented Algebraic Fault Attack Framework with Multiple Fault Injection Support.
Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
2018
Microprocess. Microsystems, 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
IEEE Embed. Syst. Lett., 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 12th European Workshop on Microelectronics Education, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Proceedings of the PROOFS 2018, 2018
2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Computers, 2016
Proceedings of the 24th European Signal Processing Conference, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the Reversible Computation - 7th International Conference, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Precise Fault-Injections using Voltage and Temperature Manipulation for Differential Cryptanalysis.
IACR Cryptol. ePrint Arch., 2014
IACR Cryptol. ePrint Arch., 2014
Proceedings of the 2014 IEEE International Conference on Wireless for Space and Extreme Environments, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the Reversible Computation - 6th International Conference, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Protecting cryptographic hardware against malicious attacks by nonlinear robust codes.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Technische Informatik in der universitären Lehre: Bestandsaufnahme, Herausforderungen, Perspektiven.
Proceedings of the Aspekte der Technischen Informatik, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012
Session Summary I: Quantum informatics: Classical circuit synthesis, resource optimisation and benchmarking.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Dependable Secur. Comput., 2011
IEEE Des. Test Comput., 2011
An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Fault Models and Test Algorithms for Nanoscale Technologies (Fehlermodelle und Testalgorithmen für Nanoscale-Technologien).
it Inf. Technol., 2010
Int. J. Parallel Program., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2010 East-West Design & Test Symposium, 2010
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Analysis and optimization of fault-tolerant embedded systems with hardened processors.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model.
Proceedings of the 2008 IEEE International Test Conference, 2008
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
J. Electron. Test., 2007
CoRR, 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it Inf. Technol., 2006
J. Electron. Test., 2006
Proceedings of the 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications).
it Inf. Technol., 2005
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Bounded Model Checking and Inductive Verification of Hybrid Discrete-continuous Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Integr., 2003
J. Electron. Test., 2003
Reducing ATE Cost in System-on-Chip Test.
Proceedings of the IFIP VLSI-SoC 2003, 2003
The Case for 2-POF.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003
Proceedings of the Ausgezeichnete Informatikdissertationen 2003, 2003
Proceedings of the 2003 Design, 2003
2002
Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
1999
Proceedings of the 4th European Test Workshop, 1999