Abhijit Chatterjee

Affiliations:
  • Georgia Institute of Technology, Atlanta, USA


According to our database1, Abhijit Chatterjee authored at least 401 papers between 1987 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Awards

IEEE Fellow

IEEE Fellow 2007, "For contributions to testing analog and mixed signal circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Effects of Measurement Uncertainties on Multitarget Tracking.
IEEE Instrum. Meas. Mag., 2022

TPMD toolkit: A toolkit for studying rate processes using molecular dynamics trajectories and performing temperature programmed molecular dynamics calculations.
Comput. Phys. Commun., 2022

Gaussian Control Barrier Functions : A Non-Parametric Paradigm to Safety.
CoRR, 2022

Self-Aware MIMO Beamforming Systems: Dynamic Adaptation to Channel Conditions and Manufacturing Variability.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding.
IEEE Trans. Dependable Secur. Comput., 2021

High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems.
J. Electron. Test., 2021

An algorithm for estimating kinetic parameters of atomistic rare events using finite-time temperature programmed molecular dynamics trajectories.
Comput. Phys. Commun., 2021

TESDA: Transform Enabled Statistical Detection of Attacks in Deep Neural Networks.
CoRR, 2021

eCloud: A Vision for the Evolution of the Edge-Cloud Continuum.
Computer, 2021

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous Vehicles.
Proceedings of the IEEE International Test Conference, 2021

Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State Checksums.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Addressing Soft Error and Security Threats in DNNs Using Learning Driven Algorithmic Checks.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Safety Uncertainty in Control Barrier Functions using Gaussian Processes.
Proceedings of the IEEE International Conference on Robotics and Automation, 2021

Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Diagnosis and Compensation of Control Program, Sensor and Actuator Failures in Nonlinear Systems Using Hierarchical State Space Checks.
J. Electron. Test., 2020

Online Parameter Estimation for Safety-Critical Systems with Gaussian Processes.
CoRR, 2020

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
Proceedings of the IEEE International Test Conference, 2020

Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks.
Proceedings of the IEEE International Test Conference, 2020

Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning.
Proceedings of the IEEE International Test Conference, 2020

Multi-Sparse Gaussian Process: Learning based Semi-Parametric Control.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

Encoded Check Driven Concurrent Error Detection in Particle Filters for Nonlinear State Estimation.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Diagnosing Software Faults Using Multiverse Analysis.
Proceedings of the Twenty-Ninth International Joint Conference on Artificial Intelligence, 2020

Gaussian Control Barrier Functions: Safe Learning and Control.
Proceedings of the 59th IEEE Conference on Decision and Control, 2020

Barrier Functions in Cascaded Controller: Safe Quadrotor Control.
Proceedings of the 2020 American Control Conference, 2020

2019
ALERA: Accelerated Reinforcement Learning Driven Adaptation to Electro-Mechanical Degradation in Nonlinear Control Systems Using Encoded State Space Error Signatures.
ACM Trans. Intell. Syst. Technol., 2019

Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition.
J. Electron. Test., 2019

Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.
Proceedings of the IEEE International Test Conference, 2019

Hierarchical Check Based Detection and Diagnosis of Sensor-Actuator Malfunction in Autonomous Systems: A Quadcopter Study.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Closed-Loop Multi-Satellite Scheduling Based on Hierarchical MDP.
Proceedings of the 22th International Conference on Information Fusion, 2019

Hierarchical State Space Checks for Errors in Sensors, Actuators and Control of Nonlinear Systems: Diagnosis and Compensation.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Content-Aware Low-Complexity Object Detection for Tracking Using Adaptive Compressed Sensing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Error Resilient Neuromorphic Networks Using Checker Neurons.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Cross-Layer Control Adaptation for Autonomous System Resilience.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

A Monobit Built-In Test and Diagnostic System for Flexible Electronic Interconnect.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Error-Resilient Video Encoding Using Parallel Independent Signature Processing.
IEEE Trans. Circuits Syst. Video Technol., 2017

Self-Learning RF Receiver Systems: Process Aware Real-Time Adaptation to Channel Conditions for Low Power Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

On-line diagnosis and compensation for parametric failures in linear state variable circuits and systems using time-domain checksum observers.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Post-Silicon Validation: Automatic Characterization of RF Device Nonidealities via Iterative Learning Experiments on Hardware.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization.
Proceedings of the IEEE International Test Conference, 2017

Probabilistic error detection and correction in switched capacitor circuits using checksum codes.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Design of efficient error resilience in signal processing and control systems: From algorithms to circuits.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Real-time self-learning for control law adaptation in nonlinear systems using encoded check states.
Proceedings of the 22nd IEEE European Test Symposium, 2017

BISCC: Efficient pre through post silicon validation of mixed-signal/RF systems using built in state consistency checking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Digitally Assisted Built-In Tuning Using Hamming Distance Proportional Signatures in RF Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Real-time DC motor error detection and control compensation using linear checksums.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Adaptive testing of analog/RF circuits using hardware extracted FSM models.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Checksum based error detection in linearized representations of non linear control systems.
Proceedings of the 17th Latin-American Test Symposium, 2016

DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems.
Proceedings of the 2016 IEEE International Test Conference, 2016

Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states.
Proceedings of the 2016 IEEE International Test Conference, 2016

Trojan detection in digital systems using current sensing of pulse propagation in logic gates.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Noise-Resilient SRAM Physically Unclonable Function Design for Security.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog Circuits.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Incoherent Undersampling-Based Waveform Reconstruction Using a Time-Domain Zero-Crossing Metric.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Automatic Test Stimulus Generation for Diagnosis of RF Transceivers Using Model Parameter Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Signature Driven Hierarchical Post-Manufacture Tuning of RF Systems for Performance and Power.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Wideband Sparse Signal Acquisition With Dual-rate Time-Interleaved Undersampling Hardware and Multicoset Signal Reconstruction Algorithms.
IEEE Trans. Signal Process., 2015

Real-Time Use-Aware Adaptive RF Transceiver Systems for Energy Efficiency Under BER Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware.
J. Electron. Test., 2015

Yield Recovery of RF Transceiver Systems Using Iterative Tuning-Driven Power-Conscious Performance Optimization.
IEEE Des. Test, 2015

Low cost high frequency signal synthesis: Application to RF channel interference testing.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

A Noise Aware CML Latch Modelling for Large System Simulation.
Proceedings of the 28th International Conference on VLSI Design, 2015

Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control.
Proceedings of the 28th International Conference on VLSI Design, 2015

"Safe" built-in test and tuning of boost converters using feedback loop perturbations.
Proceedings of the 16th Latin-American Test Symposium, 2015

Self-awareness and self-learning for resiliency in real-time systems.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Concurrent error detection in nonlinear digital filters using checksum linearization and residue prediction.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Self Learning Analog/Mixed-Signal/RF Systems: Dynamic Adaptation to Workload and Environmental Uncertainties.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

An FPGA-based ATE extension module for low-cost multi-GHz memory test.
Proceedings of the 20th IEEE European Test Symposium, 2015

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Timing Noise Characterization of High-Speed Digital Bit Sequences Using Incoherent Subsampling and Algorithmic Clock Recovery.
IEEE Trans. Instrum. Meas., 2014

Process-Variation Tolerant Channel-Adaptive Virtually Zero-Margin Low-Power Wireless Receiver Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters.
J. Electron. Test., 2014

Low Cost Signal Reconstruction Based Testing of RF Components using Incoherent Undersampling.
J. Electron. Test., 2014

Alternative "safe" test of hysteretic power converters.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A self-tuning architecture for buck converters based on alternative test.
Proceedings of the 2014 International Test Conference, 2014

Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signals.
Proceedings of the 2014 International Test Conference, 2014

3D-ICs with self-healing capability for thermal effects in RF circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Self-learning MIMO-RF receiver systems: process resilient real-time adaptation to channel conditions for low power operation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Design of low cost fault tolerant analog circuits using real-time learned error compensation.
Proceedings of the 19th IEEE European Test Symposium, 2014

High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Error Resilient Real-Time State Variable Systems for Signal Processing and Control.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A cluster expansion model for predicting activation barrier of atomic processes.
J. Comput. Phys., 2013

Dynamic Specification Testing and Diagnosis of High-Precision Sigma-Delta ADCs.
IEEE Des. Test, 2013

RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuning.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsampling.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

VAST: Post-Silicon VAlidation and Diagnosis of RF/Mixed-Signal Circuits Using Signature Tests.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Adaptive RF Front-end Design via Self-discovery: Using Real-time Data to Optimize Adaptation Control.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Adaptive MIMO RF systems: Post-manufacture and real-time tuning for performance maximization and power minimization.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Predicting die-level process variations from wafer test data for analog devices: A feasibility study.
Proceedings of the 14th Latin American Test Workshop, 2013

An adaptive class-E power amplifier with improvement in efficiency, reliability and process variation tolerance.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Real-time checking of linear control systems using analog checksums.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters.
Proceedings of the 18th IEEE European Test Symposium, 2013

Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling.
Proceedings of the Design, Automation and Test in Europe, 2013

Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Built-In Test of Switched-Mode Power Converters: Avoiding DUT Damage Using Alternative Safe Measurements.
Proceedings of the 22nd Asian Test Symposium, 2013

Analog Sensor Based Testing of Phase-Locked Loop Dynamic Performance Parameters.
Proceedings of the 22nd Asian Test Symposium, 2013

Time Domain Reconstruction of Incoherently Undersampled Periodic Waveforms Using Bandwidth Interleaving.
Proceedings of the 22nd Asian Test Symposium, 2013

Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Phase Distortion to Amplitude Conversion-Based Low-Cost Measurement of AM-AM and AM-PM Effects in RF Power Amplifiers.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Low Cost EVM Testing of Wireless RF SoC Front-Ends Using Multitones.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting.
J. Electron. Test., 2012

Concurrent Device/Specification Cause-Effect Monitoring for Yield Diagnosis Using Alternate Diagnostic Signatures.
IEEE Des. Test Comput., 2012

Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolution.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noise.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Real-Time, Content Aware Camera - Algorithm - Hardware Co-Adaptation for Minimal Power Video Encoding.
Proceedings of the 25th International Conference on VLSI Design, 2012

Power Aware Post-Manufacture Tuning of MIMO Receiver Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012

Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters.
Proceedings of the 2012 IEEE International Test Conference, 2012

Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization.
Proceedings of the 2012 IEEE International Test Conference, 2012

Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling.
Proceedings of the 2012 IEEE International Test Conference, 2012

A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Low-power adaptive RF system design using real-time fuzzy noise-distortion control.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Validation signature testing: A methodology for post-silicon validation of analog/mixed-signal circuits.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Testing of digitally assisted adaptive analog/RF systems using tuning knob - Performance space estimation.
Proceedings of the 17th IEEE European Test Symposium, 2012

Spectral Estimation Based Acquisition of Incoherently Under-sampled Periodic Signals: Application to Bandwidth Interleaving.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Environment-Adaptive Concurrent Companding and Bias Control for Efficient Power-Amplifier Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Guided Probabilistic Checksums for Error Control in Low-Power Digital Filters.
IEEE Trans. Computers, 2011

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signatures.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Accurate signature driven power conscious tuning of RF systems using hierarchical performance models.
Proceedings of the 2011 IEEE International Test Conference, 2011

Orthogonally tunable inductorless RF LNA for adaptive wireless systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate control.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation.
Proceedings of the 16th European Test Symposium, 2011

Power Aware Post-manufacture Tuning of Analog Nanocircuits.
Proceedings of the 16th European Test Symposium, 2011

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Time Domain Characterization and Test of High Speed Signals Using Incoherent Sub-sampling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Production Realization of MTPR Test on Low-Cost ATE for OFDM Based Communication Devices.
J. Electron. Test., 2010

Low-Cost Specification Based Testing of RF Amplifier Circuits using Oscillation Principles.
J. Electron. Test., 2010

Analog Signature- Driven Postmanufacture Multidimensional Tuning of RF Systems.
IEEE Des. Test Comput., 2010

A holistic approach to accurate tuning of RF systems for large and small multiparameter perturbations.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Low cost test and tuning of RF circuits and systems.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Error resilient video encoding using Block-Frame Checksums.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Built-in performance monitoring of mixed-signal/RF front ends using real-time parameter estimation.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance.
Proceedings of the 15th European Test Symposium, 2010

Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Amplitude Modulated Stimulus.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Efficient EVM Testing of Wireless OFDM Transceivers Using Null Carriers.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Accurate Linear Model for SET Critical Charge Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Checksum-Based Probabilistic Transient-Error Compensation for Linear Digital Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Environment and Process Adaptive Low Power Wireless Baseband Signal Processing Using Dual Real-Time Feedback.
J. Low Power Electron., 2009

Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations.
Proceedings of the 2009 IEEE International Test Conference, 2009

Aggressively voltage overscaled adaptive RF systems using error control at the bit and symbol levels.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Iterative built-in testing and tuning of mixed-signal/RF systems.
Proceedings of the 27th International Conference on Computer Design, 2009

Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation.
Proceedings of the 14th IEEE European Test Symposium, 2009

BIST assisted wideband digital compensation for MB-UWB transmitters.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Cognitive self-adaptive computing and communication systems: Test, control and adaptation.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

A novel self-healing methodology for RF Amplifier circuits based on oscillation principles.
Proceedings of the Design, Automation and Test in Europe, 2009

BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Low Cost Dynamic Test Methodology for High Precision ΣD ADCs.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Self-Calibrating Embedded RF Down-Conversion Mixers.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Built-in Test Enabled Diagnosis and Tuning of RF Transmitter Systems.
VLSI Design, 2008

System-Level Specification Testing Of Wireless Transceivers.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Multidimensional Adaptive Power Management for Low-Power Operation of Wireless Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Linearity Testing of A/D Converters Using Selective Code Measurement.
J. Electron. Test., 2008

Performance-Optimized Design for Parametric Reliability.
J. Electron. Test., 2008

Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers.
IEEE Des. Test Comput., 2008

Fast Accurate Tests for Multi-Carrier Transceiver Specifications: EVM and Noise.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Test Enabled Process Tuning for Adaptive Baseband OFDM Processor.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

ACT: Adaptive Calibration Test for Performance Enhancement and Increased Testability of Wireless RF Front-Ends.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms.
Proceedings of the 2008 IEEE International Test Conference, 2008

Design of process variation tolerant radio frequency low noise amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters.
Proceedings of the 13th European Test Symposium, 2008

Digital bit stream jitter testing using jitter expansion.
Proceedings of the Design, Automation and Test in Europe, 2008

Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems.
Proceedings of the 45th Design Automation Conference, 2008

Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
Signature Testing of Analog and RF Circuits: Algorithms and Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption.
J. Low Power Electron., 2007

Low-cost parametric test and diagnosis of RF systems using multi-tone response envelope detection.
IET Comput. Digit. Tech., 2007

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters.
J. Electron. Test., 2007

Alternate Diagnostic Testing and Compensation of RF Transmitter Performance Using Response Detection.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Novel Cross-Loopback Based Test Approach for Specification Test of Multi-Band, Multi-Hardware Radios.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Enhanced Resolution Jitter Testing Using Jitter Expansion.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Feedback Driven Adaptive Power Management for Minimum Power Operation of Wireless Receivers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

VIZOR: Virtually zero margin adaptive RF for ultra low power wireless communication.
Proceedings of the 25th International Conference on Computer Design, 2007

Fault-based alternate test of RF components.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.
IEEE Trans. Very Large Scale Integr. Syst., 2006

An Accurate DNA Sensing and Diagnosis Methodology Using Fabricated Silicon Nanopores.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.
J. Electron. Test., 2006

A DFT Approach for Testing Embedded Systems Using DC Sensors.
IEEE Des. Test Comput., 2006

Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Low-Cost Production Testing of Wireless Transmitters.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation.
Proceedings of the 2006 IEEE International Test Conference, 2006

On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Application of the Reactivity Index to Propose Intra and Intermolecular Reactivity in Catalytic Materials.
Proceedings of the Computational Science, 2006

Low Cost Parametric Failure Diagnosis of RF Transceivers.
Proceedings of the 11th European Test Symposium, 2006

Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test.
Proceedings of the 11th European Test Symposium, 2006

Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study.
Proceedings of the 11th European Test Symposium, 2006

Adaptive Design for Performance-Optimized Robustness.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Optimized wafer-probe and assembled package test design for analog circuits.
ACM Trans. Design Autom. Electr. Syst., 2005

Test generation for specification test of analog circuits using efficient test response observation methods.
Microelectron. J., 2005

Pseudo Dual Supply Voltage Domino Logic Design.
J. Low Power Electron., 2005

Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications.
J. Electron. Test., 2005

Time accelerated Monte Carlo simulations of biological networks using the binomial r-leap method.
Bioinform., 2005

Low-Cost Alternate EVM Test for Wireless Receiver Systems.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Production Test Methods for Measuring 'Out-of-Band' Interference of Ultra Wide Band (UWB) Devices.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Built-In Test of RF Components Using Mapped Feature Extraction Sensors.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A System-Level Alternate Test Approach for Specification Test of RF Transceivers in Loopback Mode.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Panel synopsis: reducing high-speed/RF test cost: guaranteed by design or guaranteed to fail?
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Test time reduction of successive approximation register A/D converter by selective code measurement.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Production test enhancement techniques for MB-OFDM ultra-wide band (UWB) devices: EVM and CCDF.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

This paper presents a cost-effective area-IO DRAM A CAD Tool and Algorithms.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST).
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers.
Proceedings of the 10th European Test Symposium, 2005

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits.
Proceedings of the 2005 Design, 2005

Prototyping an Embedded Bus-Based Parallel System.
Proceedings of the 20th International Conference on Computers and Their Applications, 2005

Robust Built-In Test of RF ICs Using Envelope Detectors.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Low-cost Production Test of BER for Wireless Receivers.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Low-power domino circuits using NMOS pull-up on off-critical paths.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Distributed Diagnosis of Interconnections in SoC and MCM Designs.
J. Electron. Test., 2004

Prediction of Analog Performance Parameters Using Oscillation Based Test.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

System-level Testing of RF Transmitter Specifications Using Optimized Periodic Bitstreams.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Concurrent RF Test Using Optimized Modulated RF Stimuli.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Adaptive response surface modeling-based method for analog circuit sizing.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Low-power dual V<sub>th</sub> pseudo dual V<sub>dd</sub> domino circuits.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Use of Embedded Sensors for Built-In-Test of RF Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Sizing CMOS Circuits for Increased Transient Error Tolerance.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits.
Proceedings of the 9th European Test Symposium, 2004

Test Time Reduction for ACPR Measurement of Wireless Transceivers Using Periodic Bit-Stream Sequences.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit.
Proceedings of the 2004 Design, 2004

Optically Interconnected Intelligent RAM Multiprocessor: Gigascale Opto-IRAM.
Proceedings of the 19th International Conference on Computers and Their Applications, 2004

Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Concurrent transient fault simulation for analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

High Coverage Analog Wafer-Probe Test Design and Co-optimization with Assembled-Package Test to Minimize Overall Test Cost.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Free-Space Optical Interconnect for High-Performance MCM Systems.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Seamless Research Between Academia And Industry To Facilitate Test Of Integrated High-Speed Wireless Systems: Is This An Illusion?
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

IC Reliability Simulator ARET and Its Application in Design-for-Reliability.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Prediction of analog performance parameters using fast transienttesting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Measuring Stray Capacitance on Tester Hardware.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

HA<sup>2</sup>TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Constrained Specification-Based Test Stimulus Generation for Analog Circuits Using Nonlinear Performance Prediction Models.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

A Signature Test Framework for Rapid Production Testing of RF Circuits.
Proceedings of the 2002 Design, 2002

2001
Switching activity generation with automated BIST synthesis forperformance testing of interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Path delay fault diagnosis in combinational circuits with implicitfault enumeration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures.
IEEE Trans. Computers, 2001

Hierarchical Diagnosis of Identical Units in a System.
IEEE Trans. Computers, 2001

A high-resolution jitter measurement technique using ADC sampling.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Efficient instruction-level optimization methodology for low-power embedded systems.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Test generation based diagnosis of device parameters for analog circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Specification Based Digital Compatible Built-in Test of Embedded Analog Circuits.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Specification-driven test generation for analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling.
IEEE Des. Test Comput., 2000

Test Generation for Accurate Prediction of Analog Specifications.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Optimal INL/DNL testing of A/D converters using a linear model.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog Circuits.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Test generation for fault isolation in analog circuits using behavioral models.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives.
J. VLSI Signal Process., 1999

Single-probe traversal optimization for testing of MCM substrate interconnections.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.
J. Electron. Test., 1999

Hierarchical Test Generation for Analog Circuits Using Incremental Test Development.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Efficient Test Generation for Transient Testing of Analog Circuits Using Partial Numerical Simulation.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Manufacturability of Mixed Signal Systems.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Test Generation for Analog Circuits Using Partial Numerical Simulation.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Diagnostic Test Pattern Generation for Analog Circuits Using Hierarchical Models.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

On-line fault detection in DSP circuits using extrapolated checksums with minimal test points.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

A novel concurrent fault simulation method for mixed-signal circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Fault modeling and fault sampling for isolating faults in analog and mixed-signal circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Efficient diagnosis of path delay faults in digital logic circuits.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Robust optimization based backtrace method for analog circuits.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Minimal Length Diagnostic Tests for Analog Circuits using Test History.
Proceedings of the 1999 Design, 1999

Parametric Fault Diagnosis for Analog Systems Using Functional Mapping.
Proceedings of the 1999 Design, 1999

Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1998
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis.
J. VLSI Signal Process., 1998

Signature analysis for analog and mixed-signal circuit test response compaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Testing NASA's 3D-Stack MCM Space Flight Computer.
IEEE Des. Test Comput., 1998

Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

A distributed BIST technique for diagnosis of MCM interconnections.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A high throughput test methodology for MCM substrates.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fault detection and automated fault diagnosis for embedded integrated electrical passives.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Synthesis of BIST hardware for performance testing of MCM interconnections.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

CONCERT: a concurrent transient fault simulator for nonlinear analog circuits.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Specification-Driven Test Design for Analog Circuits.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization.
IEEE Trans. Computers, 1997

A Survey of Test Techniques for MCM Substrates.
J. Electron. Test., 1997

Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

FLYER: Fast Fault Simulation of Linear Analog Circuits Using Polynomial Waveform and Perturbed State Representation.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Impact of Partial Reset on Fault Independent Testing and BIST.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Test generation for comprehensive testing of linear analog circuits using transient response sampling.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks.
Proceedings of the 34st Conference on Design Automation, 1997

1996
A unified approach for fault simulation of linear mixed-signal circuits.
J. Electron. Test., 1996

DC Built-In Self-Test for Linear Analog Circuits.
IEEE Des. Test Comput., 1996

Low-cost diagnosis of defects in MCM substrate interconnections.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Hierarchical Probablistic Diagnosis of MCMs on Large-Area Substrates.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Low-cost DC built-in self-test of linear analog circuits using checksums.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Optimal single probe traversal algorithm for testing of MCM substrat.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Relay Propagation Scheme for Testing of MCMs on Large Area Substrates.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A submicron DC MOSFET model for simulation of analog circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Efficient multisine testing of analog circuits.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Distributed Probabilistic Diagnosis of MCMs on Large Area.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

A Novel Low-Cost Approach to MCM Interconnect Test.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Guest Editors' Introduction: Low-Power VLSI Design.
IEEE Des. Test Comput., 1994

Design for diagnosability of linear digital filters using time-space expansion.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Synthesis of Low Power Linear DSP Circuits Using Activity Metrics.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A Signature Analyzer for Analog and Mixed-signal Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Greedy hardware optimization for linear digital circuits using number splitting and refactorization.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums.
IEEE Trans. Very Large Scale Integr. Syst., 1993

The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques.
IEEE Trans. Computers, 1993

Visualization in linear programming using parallel coordinates.
Pattern Recognit., 1993

Fault simulation of linear analog circuits.
J. Electron. Test., 1993

Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting.
Proceedings of the Sixth International Conference on VLSI Design, 1993

MIXER: Mixed-Signal Fault Simulator.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Fault-based automatic test generator for linear analog circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

DRAFTS: Discretized Analog Circuit Fault Simulator.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Delay fault testing of iterative arithmetic arrays.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Checksum-based concurrent error detection in linear analog systems with second and higher order stages.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

A New Approach to Fault-Tolerance in Linear Analog Systems Based on Checksum-Coded State Space Representations.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Automatic test generation for linear digital systems with bi-level search using matrix transform methods.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model.
IEEE Trans. Computers, 1991

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.
J. Electron. Test., 1991

A Rapid-Prototyping Environment for Digital-Signal Processors.
IEEE Des. Test Comput., 1991

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.
Digit. Signal Process., 1991

Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Concurrent Error Detection and Fault-Tolerance in Linear Digital State Variable Systems.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990
The Testability of Generalized Counters Under Multiple Faulty Cells.
IEEE Trans. Computers, 1990

Rapid prototyping using high density interconnects.
Proceedings of the European Design Automation Conference, 1990

A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988
A submicron MOSFET model for simulation of analog circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

NCUBE: an automatic test generation program for iterative logic arrays.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
On the C-Testability of Generalized Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987


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