Raviteja P. Reddy

According to our database, Raviteja P. Reddy authored at least 5 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Hierarchical Fault-Tolerant and Cost Effective Framework for RRAM Based Neural Computing Systems.

Chandrasekhara Srinivas Vatti, Rakesh M. B., Raviteja P. Reddy, Amit Acharyya

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2020

A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design.

Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed

IEEE Trans. Circuits Syst., 2020

2019

A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors.

Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed

Proceedings of the IEEE International Test Conference in Asia, 2019

Fault Tolerance in 3D-ICs.

Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed

Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2017

A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs.

Raviteja P. Reddy, Amit Acharyya, S. Saqib Khursheed

IEEE Trans. Very Large Scale Integr. Syst., 2017