S. Saqib Khursheed

According to our database1, S. Saqib Khursheed authored at least 43 papers between 2006 and 2020.

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2020
LFSR generation for high test coverage and low hardware overhead.
IET Comput. Digit. Tech., 2020

Leveraging CMOS Aging for Efficient Microelectronics Design.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Secure Scan Design with a Novel Methodology of Scan Camouflaging.
Proceedings of the European Conference on Circuit Theory and Design, 2020

2019
A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2019

Fault Tolerance in 3D-ICs.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Recycled IC detection through aging sensor.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Aging Benefits in Nanometer CMOS Designs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing.
J. Low Power Electron., 2017

Welcome Message.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016
Reliable Power Gating With NBTI Aging Benefits.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Guest Editors' Introduction: Robust 3-D Stacked ICs.
IEEE Des. Test, 2016

Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Reconfigurable hardware-software codesign methodology for protein identification.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
Online Fault Tolerance Technique for TSV-Based 3-D-IC.
IEEE Trans. Very Large Scale Integr. Syst., 2015

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Application-specific memory protection policies for energy-efficient reliable design.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Diagnosis of power switches with power-distribution-network consideration.
Proceedings of the 20th IEEE European Test Symposium, 2015

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Delay Test for Diagnosis of Power Switches.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

High Quality Testing of Grid Style Power Gating.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Impact of PVT variation on delay test of resistive open and resistive bridge defects.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2011
A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Improved DFT for Testing Power Switches.
Proceedings of the 16th European Test Symposium, 2011

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Test and diagnosis of resistive bridges in multi-Vdd designs.
PhD thesis, 2010

Gate-Sizing-Based Single V<sub>dd</sub> Test for Bridge Defects in Multivoltage Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Modeling the impact of process variation on resistive bridge defects.
Proceedings of the 2011 IEEE International Test Conference, 2010

Scan based methodology for reliable state retention power gating designs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Diagnosis of Multiple-Voltage Design With Bridge Defect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Process Variation-Aware Test for Resistive Bridges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Bridging Fault Test Method With Adaptive Power Management Awareness.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Bridge Defect Diagnosis for Multiple-Voltage Design.
Proceedings of the 13th European Test Symposium, 2008

2007
Efficient test compaction for combinational circuits based on Fault detection count-directed clustering.
IET Comput. Digit. Tech., 2007

2006
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006


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