Reiner Kolla
According to our database1,
Reiner Kolla
authored at least 37 papers
between 1983 and 2017.
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Bibliography
2017
TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips.
Journal of Systems Architecture - Embedded Systems Design, 2017
MCGC: A Network Coding Approach for Reliable Large-scale Wireless Networks.
Proceedings of the First ACM International Workshop on the Engineering of Reliable, 2017
2016
Using benes networks at fault-tolerant and deflection routing based network-on-chips.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Consideration of the Flit Size for Deflection Routing based Network-on-Chips.
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2016
A wearable 1-lead necklace ECG for continuous heart rate monitoring.
Proceedings of the 18th IEEE International Conference on e-Health Networking, 2016
An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2011
Precise self-calibration of ultrasound based indoor localization systems.
Proceedings of the 2011 International Conference on Indoor Positioning and Indoor Navigation, 2011
2007
Beyond Theory: Development of a Real World Localization Application as Low Power WSN.
Proceedings of the 32nd Annual IEEE Conference on Local Computer Networks (LCN 2007), 2007
A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot.
Proceedings of the 32nd Annual IEEE Conference on Local Computer Networks (LCN 2007), 2007
2003
Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers.
IEEE Trans. Computers, 2003
2002
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures.
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
Bubble Partitioning for LUT-Based Sequential Circuits.
Proceedings of the Field-Programmable Logic and Applications, 2001
2000
Technology Binding.
Informatik Spektrum, 2000
A New Floorplanning Method for FPGA Architectural Research.
Proceedings of the Field-Programmable Logic and Applications, 2000
1999
Spanning Tree-based State Encoding for Low Power Dissipation.
Proceedings of the 1999 Design, 1999
Splitting Double Precision FPUs for Single Precision Interval Arithmetic.
Proceedings of the Workshops zur Architektur von Rechensystemen, 1999
1998
PACE: Processor Architectures for Circuit Emulation.
IPPS/SPDP Workshops, 1998
Boolean Matching for Large Libraries.
Proceedings of the 35th Conference on Design Automation, 1998
1997
Node normalization and decomposition in low power technology mapping.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
A parallel hybrid approach to hard optimization problems.
Proceedings of the Architektur von Rechensystemen, Arbeitsteilige Systemarchitekturen: Konzepte, Lösungen, Anwendungen, Trends, 1997
1996
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
1995
Optimal technology mapping for single output cells.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995
1992
A cell-based approach to performance optimization of fanout-free circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992
1991
The Virtual Feedback Problem in Hierarchical Representations of Combinational Circuits.
Acta Inf., 1991
1990
Minimal Area Sizing of Power Supply Nets in VLSI Circuits.
Elektronische Informationsverarbeitung und Kybernetik, 1990
A dynamic programming approach to the power supply net sizing problem.
Proceedings of the European Design Automation Conference, 1990
Cell based performance optimization of combinational circuits.
Proceedings of the European Design Automation Conference, 1990
A graphical system for hierarchical specifications and checkups of VLSI circuits.
Proceedings of the European Design Automation Conference, 1990
1989
A note on hierarchical layer-assignment.
Integration, 1989
Einführung in den VLSI-Entwurf.
Leitfäden und Monographien der Informatik, Teubner, ISBN: 978-3-519-02273-2, 1989
1988
On the Construction of Optimal Time Adders (Extended Abstract).
Proceedings of the STACS 88, 1988
1987
Spezifikation und Expansion logisch-topologischer Netze.
PhD thesis, 1987
Hierarchical Design Based on a Calculus of Nets.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987
1986
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform., Forsch. Entwickl., 1986
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform., Forsch. Entwickl., 1986
On Network Algebras and Recursive Equations.
Proceedings of the Graph-Grammars and Their Application to Computer Science, 1986
1983
Where-Oblivious is not Sufficient.
Inf. Process. Lett., 1983