Paul Molitor

Orcid: 0000-0003-1461-7936

Affiliations:
  • Martin Luther University of Halle-Wittenberg, Germany


According to our database1, Paul Molitor authored at least 77 papers between 1986 and 2023.

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Bibliography

2023
Machine learning applications.
it Inf. Technol., August, 2023

LERA - an interactive platform for synoptical representations of multiple text witnesses.
Digit. Scholarsh. Humanit., April, 2023

2022
Putting collation of text witnesses on a formal basis.
Digit. Scholarsh. Humanit., 2022

2020
Fast paraphrase extraction in Ancient Greek literature.
it Inf. Technol., 2020

Digital methods for intertextuality studies.
it Inf. Technol., 2020

Keter Shem Ṭov - Prozessualisierung eines Editionsprojekts mit 100 Textzeugen.
Proceedings of the 7. Tagung des Verbands Digital Humanities im deutschsprachigen Raum, 2020

2018
Finding the Redundant Gates in Reversible Circuits.
Proceedings of the Reversible Computation - 10th International Conference, 2018

2015
An optimized platform for capturing metadata of historical correspondence.
Digit. Scholarsh. Humanit., 2015

Reviewers 2013-2014.
it Inf. Technol., 2015

Differenzanalyse komplexer Textvarianten - Diskussion und Werkzeuge.
Datenbank-Spektrum, 2015

"im Zentrum eines Netzes [...] geistiger Fäden". Erschließung und Erforschung thematischer Zusammenhänge in heterogenen Briefkorpora.
Datenbank-Spektrum, 2015

Computational Recognition of RNA Splice Sites by Exact Algorithms for the Quadratic Traveling Salesman Problem.
Comput., 2015

2014
Preface.
it Inf. Technol., 2014

A backbone based TSP heuristic for large instances.
J. Heuristics, 2014

Exact algorithms and heuristics for the Quadratic Traveling Salesman Problem with an application in bioinformatics.
Discret. Appl. Math., 2014

User-friendly lemmatization and morphological annotation of Early New High German manuscripts.
Proceedings of the 9th Annual International Conference of the Alliance of Digital Humanities Organizations, 2014

2013
Model Checking for PLC based Railway Interlocking Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Optimized platform for capturing metadata of historical correspondences.
Proceedings of the 8th Annual International Conference of the Alliance of Digital Humanities Organizations, 2013

2011
Reviewer Thanks.
it Inf. Technol., 2011

BDD-based Analysis of Test Cases for PLC-based Railway Interlocking Systems.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

2010
Finding Good Tours for Huge Euclidean TSP Instances by Iterative Backbone Contraction.
Proceedings of the Algorithmic Aspects in Information and Management, 2010

2009
Effective Heuristics for Large Euclidean TSP Instances Based on Pseudo Backbones.
Proceedings of the 8th Cologne-Twente Workshop on Graphs and Combinatorial Optimization, 2009

Effective Tour Searching for TSP by Contraction of Pseudo Backbone Edges.
Proceedings of the Algorithmic Aspects in Information and Management, 2009

2008
Gutachter 2008.
it Inf. Technol., 2008

Algorithms and Experimental Study for the Traveling Salesman Problem of Second Order.
Proceedings of the Combinatorial Optimization and Applications, 2008

Technische Informatik - eine einführende Darstellung.
Oldenbourg, ISBN: 978-3-486-58650-3, 2008

2007
What Graphs can be Efficiently Represented by BDDs?
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Improving the Efficiency of Helsgaun's Lin-Kernighan Heuristic for the Symmetric TSP.
Proceedings of the Combinatorial and Algorithmic Aspects of Networking, 4th Workshop, 2007

2006
...was wird mit übrigens?
it Inf. Technol., 2006

Tolerance Based Contract-or-Patch Heuristic for the Asymmetric TSP.
Proceedings of the Combinatorial and Algorithmic Aspects of Networking, Third Workshop, 2006

Some Basics on Tolerances.
Proceedings of the Algorithmic Aspects in Information and Management, 2006

2005
Gutachter 2005.
it Inf. Technol., 2005

Technische Informatik - eine Einführung.
Pearson Studium, Pearson Education, ISBN: 978-3-8273-7092-1, 2005

2004
Gutachter 2004.
it Inf. Technol., 2004

VHDL - eine Einführung.
Pearson Studium, ISBN: 978-3-8273-7047-1, 2004

2003
Zum neuen Jahrgang.
it Inf. Technol., 2003

Polynomial Formal Verification of Multipliers.
Formal Methods Syst. Des., 2003

2002
Limits of Using Signatures for Permutation Independent Boolean Comparison.
Formal Methods Syst. Des., 2002

What are the samples for learning efficient routing heuristics? [MCM routing].
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
Application of BDDs in Boolean matching techniques for formal logic combinational verification.
Int. J. Softw. Tools Technol. Transf., 2001

A pipelined architecture for partitioned DWT based lossy image compression using FPGA's.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001

2000
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties.
IEEE Trans. Computers, 2000

Permutation Independent Comparison of Pseudo Boolean Functions.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

Prove that a faulty multiplier is faulty!?
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

<i>k</i>-Layer Straightline Crossing Minimization by Speeding Up Sifting.
Proceedings of the Graph Drawing, 8th International Symposium, 2000

A partitioned wavelet-based approach for image compression using FPGA's.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines.
Proceedings of ASP-DAC 2000, 2000

1999
BDD minimization using symmetries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Establishing latch correspondence for sequential circuits using distinguishing signatures.
Integr., 1999

Using Sifting for k -Layer Straightline Crossing Minimization.
Proceedings of the Graph Drawing, 7th International Symposium, 1999

Datenstrukturen und effiziente Algorithmen für die Logiksynthese kombinatorischer Schaltungen.
Teubner, ISBN: 978-3-519-02945-8, 1999

1998
Modeling the Communication Behavior of Distributed Memory Machines by Genetic Programming.
Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997
Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries.
Proceedings of the European Design and Test Conference, 1997

1996
New Crossover Methods For Sequencing Problems.
Proceedings of the Parallel Problem Solving from Nature, 1996

Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995
On the generation of area-time optimal testable adders.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Priority driven channel pin assignment.
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Communication based FPGA synthesis for multi-output Boolean functions.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Communication based multilevel synthesis for multi-output Boolean functions.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization.
Integr., 1993

On the implementation of an efficient performance driven generator for conditional-sum-adders.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Performance Driven k-Layer Wiring.
Proceedings of the STACS 92, 1992

A performance driven generator for efficient testable conditional-sum-adders.
Proceedings of the conference on European design automation, 1992

A Hierarchy Preserving Hierarchical Bottom-Up 2-layer Wiring Algorithm with Respect to Via Minimization.
Proceedings of the Informatik, Festschrift zum 60. Geburtstag von Günter Hotz, 1992

1991
Minimal stretching of a layout to ensure 2-layer wirability.
Integr., 1991

A Survey on Wiring.
J. Inf. Process. Cybern., 1991

1990
Constrained via minimization for systolic arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A graphical system for hierarchical specifications and checkups of VLSI circuits.
Proceedings of the European Design Automation Conference, 1990

1989
A note on hierarchical layer-assignment.
Integr., 1989

Einführung in den VLSI-Entwurf.
Leitfäden und Monographien der Informatik, Teubner, ISBN: 978-3-519-02273-2, 1989

1987
On the Contact-Minimization-Problem.
Proceedings of the STACS 87, 1987

Hierarchical Design Based on a Calculus of Nets.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Über die Bikategorie der logisch-topologischen Netze und ihre Semantik.
PhD thesis, 1986

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II.
Inform. Forsch. Entwickl., 1986

Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I.
Inform. Forsch. Entwickl., 1986

On Network Algebras and Recursive Equations.
Proceedings of the Graph-Grammars and Their Application to Computer Science, 1986


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