Reza Sedaghat
According to our database1,
Reza Sedaghat
authored at least 35 papers
between 2003 and 2022.
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Bibliography
2022
A Novel Machine Learning Framework for Covid-19 Image Classification with Bio-heuristic Optimization.
Trans. Comput. Sci., 2022
2021
Trans. Comput. Sci., 2021
Novel Hybrid GWO-WOA and BAT-PSO Algorithms for Solving Design Optimization Problems.
Trans. Comput. Sci., 2021
2019
Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis.
Swarm Evol. Comput., 2019
A New Adaptive Security Architecture with Extensible Computation Complexity for Generic Ciphers.
J. Hardw. Syst. Secur., 2019
2018
Trans. Comput. Sci., 2018
2017
intel-LEACH: An optimal framework for node selection using dynamic clustering for wireless sensor networks.
Proceedings of the 12th International Conference for Internet Technology and Secured Transactions, 2017
2016
A New Adaptable Construction of Modulo Addition with Scalable Security for Stream Ciphers.
Proceedings of the Network and System Security - 10th International Conference, 2016
An adaptive security framework with extensible computational complexity for cipher systems.
Proceedings of the 11th International Conference for Internet Technology and Secured Transactions, 2016
2015
Signal Process. Image Commun., 2015
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget.
Microelectron. Reliab., 2015
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015
2012
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.
Swarm Evol. Comput., 2012
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.
Microprocess. Microsystems, 2012
2011
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems.
Microelectron. Reliab., 2011
Microelectron. Reliab., 2011
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
Microprocess. Microsystems, 2011
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Integrated design space exploration based on power-performance trade-off using genetic algorithm.
Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.
Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011
2010
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective.
Microelectron. Reliab., 2010
Microelectron. Reliab., 2010
Microelectron. J., 2010
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies.
Microelectron. Reliab., 2009
2008
FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration.
Microelectron. Reliab., 2008
A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies.
Proceedings of the Advances in Computer Science and Engineering, 2008
2007
Microelectron. Reliab., 2007
2006
Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates.
Microelectron. Reliab., 2006
Microprocess. Microsystems, 2006
Microprocess. Microsystems, 2006
2003
A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003