Anirban Sengupta
Orcid: 0000-0002-6239-256X
According to our database1,
Anirban Sengupta
authored at least 157 papers
between 2005 and 2024.
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Bibliography
2024
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS.
Integr., March, 2024
Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework.
IEEE Access, 2024
2023
Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs.
Comput. Electr. Eng., October, 2023
IEEE Trans. Consumer Electron., August, 2023
PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesis.
Expert Syst. Appl., August, 2023
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Comput. Electr. Eng., January, 2023
IEEE Trans. Dependable Secur. Comput., 2023
Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis.
Microprocess. Microsystems, 2023
Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis.
Microprocess. Microsystems, 2023
Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Key-Driven Multi-Layered Structural Obfuscation of IP cores using Reconfigurable Obfuscator based Network Challenge and Switch Control Logic.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Fusing IP vendor Palmprint Biometric with Encoded Hash for Hardware IP Core Protection of Image Processing Filters.
Proceedings of the International Conference on Microelectronics, 2023
Secured and Optimized Hardware Accelerators using Key-Controlled Encoded Hash Slices and Firefly Algorithm based Exploration.
Proceedings of the International Conference on Microelectronics, 2023
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023
2022
Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric.
IEEE Trans. Consumer Electron., 2022
Secur. Priv., 2022
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems.
IEEE Consumer Electron. Mag., 2022
Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression.
IEEE Access, 2022
Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Behavioral Synthesis for Hardware Security, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Intell. Transp. Syst., 2021
IEEE Trans. Consumer Electron., 2021
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
NeuroImage, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
A Stakeholder-Centric Approach for Defining Metrics for Information Security Management Systems.
Proceedings of the Risks and Security of Internet and Systems, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors.
IEEE Trans. Consumer Electron., 2020
Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems.
IEEE Trans. Consumer Electron., 2020
IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems.
IEEE Trans. Consumer Electron., 2020
Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems.
IEEE Access, 2020
Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020
Proceedings of the CENTERIS 2020 - International Conference on ENTERprise Information Systems / ProjMAN 2020 - International Conference on Project MANagement / HCist 2020, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Consumer Electron., 2019
IEEE Trans. Consumer Electron., 2019
Embedding Digital Signature Using Encrypted-Hashing for Protection of DSP Cores in CE.
IEEE Trans. Consumer Electron., 2019
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].
IEEE Consumer Electron. Mag., 2019
IEEE Consumer Electron. Mag., 2019
Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware.
IEEE Access, 2019
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic.
Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019
Proceedings of the Advanced Computing and Systems for Security, 2019
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019
2018
IEEE Trans. Consumer Electron., 2018
IEEE Trans. Consumer Electron., 2018
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Aerosp. Electron. Syst., 2018
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Comput. Digit. Tech., 2018
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis.
Future Gener. Comput. Syst., 2018
IEEE Consumer Electron. Mag., 2018
Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters].
IEEE Consumer Electron. Mag., 2018
IEEE Consumer Electron. Mag., 2018
Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter].
IEEE Consumer Electron. Mag., 2018
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters].
IEEE Consumer Electron. Mag., 2018
IEEE Access, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
2017
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions.
IEEE Trans. Very Large Scale Integr. Syst., 2017
DSP design protection in CE through algorithmic transformation based structural obfuscation.
IEEE Trans. Consumer Electron., 2017
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Low cost fault tolerance against k<sub>c</sub>-cycle and k<sub>m</sub>-unit transient for loop based control data flow graphs during physically aware high level synthesis.
Microelectron. Reliab., 2017
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper).
Integr., 2017
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis.
Future Gener. Comput. Syst., 2017
Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters].
IEEE Consumer Electron. Mag., 2017
Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters].
IEEE Consumer Electron. Mag., 2017
IEEE Consumer Electron. Mag., 2017
IEEE Consumer Electron. Mag., 2017
Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection: From paper marks to hardware protection.
IEEE Consumer Electron. Mag., 2017
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools.
Adv. Eng. Softw., 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
A Quantitative Methodology for Cloud Security Risk Assessment.
Proceedings of the CLOSER 2017, 2017
2016
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.
Microelectron. Reliab., 2016
Modelling operations and security of cloud systems using Z-notation and Chinese Wall security policy.
Enterp. Inf. Syst., 2016
Soft IP Core Design Resiliency Against Terrestrial Transient Faults for CE Products [Hardware Matters].
IEEE Consumer Electron. Mag., 2016
IEEE Consumer Electron. Mag., 2016
Evolution of the IP Design Process in the Semiconductor/EDA Industry Hardware Matters.
IEEE Consumer Electron. Mag., 2016
IEEE Consumer Electron. Mag., 2016
IEEE Consumer Electron. Mag., 2016
IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access, 2016
Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.
IEEE Access, 2016
Proceedings of the Security in Computing and Communications - 4th International Symposium, 2016
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Embedding low cost optimal watermark during high level synthesis for reusable IP core protection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A Quantitative Methodology for Security Risk Assessment of Enterprise Business Processes.
Proceedings of the 2nd International Conference on Information Systems Security and Privacy, 2016
2015
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget.
Microelectron. Reliab., 2015
Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence.
Int. J. Knowl. Based Intell. Eng. Syst., 2015
Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis.
Expert Syst. Appl., 2015
Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis.
Appl. Math. Comput., 2015
Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing.
Adv. Eng. Softw., 2015
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints.
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the Security in Computing and Communications, 2015
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015
GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015
2014
Automated exploration of datapath and unrolling factor during power-performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm.
Expert Syst. Appl., 2014
A two-phase quantitative methodology for enterprise information security risk analysis.
Comput. Syst. Sci. Eng., 2014
MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design.
Adv. Eng. Softw., 2014
Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and Dispersal.
Proceedings of the 18th International Conference in Knowledge Based and Intelligent Information and Engineering Systems, 2014
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Proceedings of the Information Systems Security - 10th International Conference, 2014
Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment.
Proceedings of the 2014 International Conference on Information Technology, 2014
Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget.
Proceedings of the 2014 International Conference on Information Technology, 2014
Automated parallel exploration of datapath and Unrolling Factor in High Level Synthesis using hyper-dimensional particle swarm encoding.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014
Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014
2013
D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processors.
Proceedings of the International Conference on Advances in Computing, 2013
A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications.
Proceedings of the International Conference on Advances in Computing, 2013
Proceedings of the 2013 International Conference on Risks and Security of Internet and Systems (CRiSIS), 2013
2012
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.
Swarm Evol. Comput., 2012
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.
Microprocess. Microsystems, 2012
Proceedings of the CUBE International IT Conference & Exhibition, 2012
2011
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems.
Microelectron. Reliab., 2011
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
Microprocess. Microsystems, 2011
A Formal Methodology for Detecting Managerial Vulnerabilities and Threats in an Enterprise Information System.
J. Netw. Syst. Manag., 2011
A Mark-Up Language for the Specification of Information Security Governance Requirements.
Int. J. Inf. Secur. Priv., 2011
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 International Conference on Communication, 2011
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Integrated design space exploration based on power-performance trade-off using genetic algorithm.
Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.
Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011
2010
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective.
Microelectron. Reliab., 2010
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
A formal methodology for detection of vulnerabilities in an enterprise information system.
Proceedings of the CRiSIS 2009, 2009
2006
Proceedings of the Information Systems Security, Second International Conference, 2006
2005
A Web-Enabled Enterprise Security Management Framework Based on a Unified Model of Enterprise Information System Security .
Proceedings of the Information Systems Security, First International Conference, 2005