Anirban Sengupta

According to our database1, Anirban Sengupta authored at least 89 papers between 2005 and 2019.

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Bibliography

2019
Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices [Hardware Matters].
IEEE Consumer Electronics Magazine, 2019

Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware.
IEEE Access, 2019

2018
Low-Cost Obfuscated JPEG CODEC IP Core for Secure CE Hardware.
IEEE Trans. Consumer Electronics, 2018

Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature.
IEEE Trans. Consumer Electronics, 2018

Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath.
IEEE Trans. Aerospace and Electronic Systems, 2018

Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Computers & Digital Techniques, 2018

Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis.
Future Generation Comp. Syst., 2018

Audio and Video Technologies: Recent Advances in Consumer Electronics.
IEEE Consumer Electronics Magazine, 2018

Intellectual Property-Based Lossless Image Compression for Camera Systems [Hardware Matters].
IEEE Consumer Electronics Magazine, 2018

Optimizing DSP Cores Using Design Transformation [Hardware Matters].
IEEE Consumer Electronics Magazine, 2018

Obfuscated JPEG Image Decompression IP Core for Protecting Against Reverse Engineering [Hardware Matter].
IEEE Consumer Electronics Magazine, 2018

Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters].
IEEE Consumer Electronics Magazine, 2018

A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC.
IEEE Access, 2018

Obfuscation of Fault Secured DSP Design Through Hybrid Transformation.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Reusable intellectual property core protection for both buyer and seller.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Multi-phase watermark for IP core protection.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions.
IEEE Trans. VLSI Syst., 2017

DSP design protection in CE through algorithmic transformation based structural obfuscation.
IEEE Trans. Consumer Electronics, 2017

TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis.
Microelectronics Reliability, 2017

Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper).
Integration, 2017

Low-cost security aware HLS methodology.
IET Computers & Digital Techniques, 2017

Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis.
Future Generation Comp. Syst., 2017

Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters].
IEEE Consumer Electronics Magazine, 2017

Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters].
IEEE Consumer Electronics Magazine, 2017

Hardware Security of CE Devices [Hardware Matters].
IEEE Consumer Electronics Magazine, 2017

Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters].
IEEE Consumer Electronics Magazine, 2017

Everything You Want to Know About Watermarking: From Paper Marks to Hardware Protection: From paper marks to hardware protection.
IEEE Consumer Electronics Magazine, 2017

Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools.
Advances in Engineering Software, 2017

A Quantitative Methodology for Cloud Security Risk Assessment.
Proceedings of the CLOSER 2017, 2017

2016
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.
Microelectronics Reliability, 2016

Modelling operations and security of cloud systems using Z-notation and Chinese Wall security policy.
Enterprise IS, 2016

Soft IP Core Design Resiliency Against Terrestrial Transient Faults for CE Products [Hardware Matters].
IEEE Consumer Electronics Magazine, 2016

Cognizance on Intellectual Property: A High-Level Perspective [Hardware Matters].
IEEE Consumer Electronics Magazine, 2016

Evolution of the IP Design Process in the Semiconductor/EDA Industry Hardware Matters.
IEEE Consumer Electronics Magazine, 2016

Design Flow of a Digital IC: The role of digital IC/SOC design in CE products.
IEEE Consumer Electronics Magazine, 2016

Intellectual Property Cores: Protection designs for CE products.
IEEE Consumer Electronics Magazine, 2016

IEEE Access Special Section Editorial: Security and Reliability Aware System Design for Mobile Computing Devices.
IEEE Access, 2016

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.
IEEE Access, 2016

An Automated Methodology for Secured User Allocation in Cloud.
Proceedings of the Security in Computing and Communications - 4th International Symposium, 2016

Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Embedding low cost optimal watermark during high level synthesis for reusable IP core protection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A Quantitative Methodology for Security Risk Assessment of Enterprise Business Processes.
Proceedings of the 2nd International Conference on Information Systems Security and Privacy, 2016

2015
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget.
Microelectronics Reliability, 2015

Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence.
KES Journal, 2015

Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis.
Expert Syst. Appl., 2015

Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis.
Applied Mathematics and Computation, 2015

Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing.
Advances in Engineering Software, 2015

Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints.
Proceedings of the VLSI Design, Automation and Test, 2015

Modeling Dependencies of ISO/IEC 27002: 2013 Security Controls.
Proceedings of the Security in Computing and Communications, 2015

User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis.
Proceedings of the IEEE 28th Canadian Conference on Electrical and Computer Engineering, 2015

2014
Automated exploration of datapath and unrolling factor during power-performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm.
Expert Syst. Appl., 2014

MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design.
Advances in Engineering Software, 2014

Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and Dispersal.
Proceedings of the 18th International Conference in Knowledge Based and Intelligent Information and Engineering Systems, 2014

Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A Formal Methodology for Modeling Threats to Enterprise Assets.
Proceedings of the Information Systems Security - 10th International Conference, 2014

Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment.
Proceedings of the 2014 International Conference on Information Technology, 2014

Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget.
Proceedings of the 2014 International Conference on Information Technology, 2014

Automated parallel exploration of datapath and Unrolling Factor in High Level Synthesis using hyper-dimensional particle swarm encoding.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014

2013
D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processors.
Proceedings of the International Conference on Advances in Computing, 2013

A methodology for self correction scheme based fast multi criterion exploration and architectual synthesis of data dominated applications.
Proceedings of the International Conference on Advances in Computing, 2013

A formal methodology for Enterprise Information Security risk assessment.
Proceedings of the 2013 International Conference on Risks and Security of Internet and Systems (CRiSIS), 2013

2012
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels.
Swarm and Evolutionary Computation, 2012

Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.
Microprocessors and Microsystems - Embedded Hardware Design, 2012

Specification and validation of enterprise information security policies.
Proceedings of the CUBE International IT Conference & Exhibition, 2012

A two-phase quantitative methodology for enterprise information security risk analysis.
Proceedings of the CUBE International IT Conference & Exhibition, 2012

2011
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems.
Microelectronics Reliability, 2011

Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
Microprocessors and Microsystems - Embedded Hardware Design, 2011

A Formal Methodology for Detecting Managerial Vulnerabilities and Threats in an Enterprise Information System.
J. Network Syst. Manage., 2011

A Mark-Up Language for the Specification of Information Security Governance Requirements.
IJISP, 2011

Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A quantitative methodology for information security control gap analysis.
Proceedings of the 2011 International Conference on Communication, 2011

Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011

Integrated design space exploration based on power-performance trade-off using genetic algorithm.
Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011

Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis.
Proceedings of the International Conference on Advances in Computing and Artificial Intelligence, 2011

2010
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective.
Microelectronics Reliability, 2010

A framework for fast design space exploration using fuzzy search for VLSI computing Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Rapid design space exploration for multi parametric optimization of VLSI designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A formal methodology for detection of vulnerabilities in an enterprise information system.
Proceedings of the CRiSIS 2009, 2009

2006
Towards a Formal Specification Method for Enterprise Information System Security.
Proceedings of the Information Systems Security, Second International Conference, 2006

2005
A Web-Enabled Enterprise Security Management Framework Based on a Unified Model of Enterprise Information System Security .
Proceedings of the Information Systems Security, First International Conference, 2005


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