Riaz Naseer

According to our database, Riaz Naseer authored at least 5 papers between 2006 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2008

DEC ECC design to improve memory reliability in Sub-100nm technologies.

Riaz Naseer, Jeff Draper

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs.

Riaz Naseer, Jeff Draper

Proceedings of the ESSCIRC 2008, 2008

2007

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM.

Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.

Riaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

DF-DICE: a scalable solution for soft error tolerant circuit design.

Riaz Naseer, Jeff Draper

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006