Jeffrey T. Draper
Affiliations:- University of Southern California, Los Angeles, USA
According to our database1,
Jeffrey T. Draper
authored at least 93 papers
between 1991 and 2019.
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Bibliography
2019
HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Normalization and dropout for stochastic computing-based deep convolutional neural networks.
Integr., 2019
IET Comput. Digit. Tech., 2019
2018
Towards Budget-Driven Hardware Optimization for Deep Convolutional Neural Networks Using Stochastic Computing.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
High performance training of deep neural networks using pipelined hardware acceleration and distributed memory.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
2017
Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits.
ACM Trans. Design Autom. Electr. Syst., 2017
Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Structural design optimization for deep convolutional neural networks using stochastic computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution.
ACM Trans. Archit. Code Optim., 2016
Proceedings of the Second International Symposium on Memory Systems, 2016
Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Accelerating soft-error-rate (SER) estimation in the presence of single event transients.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the 5th Workshop on Irregular Applications - Architectures and Algorithms, 2015
Proceedings of the 2015 International Symposium on Memory Systems, 2015
Congestion-aware optimal techniques for assigning inter-tier signals to 3D-vias in a 3DIC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Microelectron. J., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A framework to quantify FPGA design hardness against radiation-induced single event effects.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Mitigating the Mismatch between the Coherence Protocol and Conflict Detection in Hardware Transactional Memory.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014
2013
IEEE Trans. Parallel Distributed Syst., 2013
Proceedings of the 1st International Workshop on Energy Efficient Supercomputing, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
SEL-TM: Selective Eager-Lazy Management for Improved Concurrency in Transactional Memory.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012
TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 39th International Conference on Parallel Processing, 2010
2009
Microelectron. J., 2009
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
The effect of design parameters on single-event upset sensitivity of MOS current mode logic.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Floating-point division and square root implementation using a Taylor-series expansion algorithm.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the ESSCIRC 2008, 2008
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
2005
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.
J. VLSI Signal Process., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Design trade-offs in floating-point unit implementation for embedded and processing-in-memory systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Performance Analysis of User-Level PIM Communication in the Data IntensiVe Architecture (DIVA) System.
Proceedings of the High Performance Computing, 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
A 0.18 µm implementation of a floating-point unit for a processing-in-memory system.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
An area-efficient standard-cell floating-point unit design for a processing-in-memory system.
Proceedings of the ESSCIRC 2003, 2003
2002
Proceedings of the 16th international conference on Supercomputing, 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
2000
Performance optimization for high-order continuous-time ΣΔ modulators with extra loop delay.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
A continuous-time common-mode feedback circuit (CMFB) for high-impedance current mode application.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
1997
Routing in Bidirectional k-ary n-cubes with the Red Rover Algorithm.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997
Proceedings of the 6th International Symposium on High Performance Distributed Computing, 1997
1996
The Red Rover Algorithm for Deadlock-Free Routing on Bidirectional Rings.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996
1994
Parallel Comput., 1994
J. Parallel Distributed Comput., 1994
1993
J. Parallel Distributed Comput., 1993
1992
Multipath E-Cube Algorithms (MECA) for Adaptive Wormhole Routing and Broadcasting in itk-ary itn-Cubes.
Proceedings of the 6th International Parallel Processing Symposium, 1992
1991
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991