Ricardo José Colom-Palero

According to our database, Ricardo José Colom-Palero authored at least 12 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Optimization of Deep Neural Networks Using SoCs with OpenCL.

Rafael Gadea Gironés, Ricardo José Colom-Palero, Vicente Herrero-Bosch

Sensors, 2018

2009

A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA.

Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch

Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008

A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding.

Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero

Microprocess. Microsystems, 2008

A Mixed Hardware/Software SOFM Training System.

Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona

Computación y Sistemas, 2008

SoC-Based Implementation of the Backpropagation Algorithm for MLP.

Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastiá, Fernando Mateo

Proceedings of the 8th International Conference on Hybrid Intelligent Systems (HIS 2008), 2008

2007

A wavelet-VQ system for real-time video compression.

Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona

J. Real Time Image Process., 2007

2006

A Novel FPGA Architecture of a 2-D Wavelet Transform.

Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés

J. VLSI Signal Process., 2006

An active methodology for teaching electronic systems design.

Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero

IEEE Trans. Educ., 2006

2005

FPGA Implementation of a Pipelined On-Line Backpropagation.

Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés

J. VLSI Signal Process., 2005

2004

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices.

Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró

Microprocess. Microsystems, 2004

FPGA Custom DSP for ECG Signal Analysis and Compression.

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer

Proceedings of the Field Programmable Logic and Application, 2004

2003

FPGA Implementation of Adaptive Non-linear Predictors for Video Compression.

Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003