Ricardo P. Jasinski

According to our database, Ricardo P. Jasinski authored at least 14 papers between 2004 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

A reliable and energy-efficient classifier combination scheme for intrusion detection in embedded systems.

Eduardo Viegas, Altair Olivo Santin, Luiz Oliveira, André França, Ricardo P. Jasinski, Volnei A. Pedroni

Comput. Secur., 2018

2017

Towards an Energy-Efficient Anomaly-Based Intrusion Detection Engine for Embedded Systems.

Eduardo Viegas, Altair Olivo Santin, André França, Ricardo P. Jasinski, Volnei A. Pedroni, Luiz S. Oliveira

IEEE Trans. Computers, 2017

2016

Extraction of spatio-temporal features based on a hardware approach for a no-reference objective video quality metric.

Marcelo de Oliveira Rosa, Caio Cesar Viana da Silva, Wyllian Bezerra da Silva, Ricardo P. Jasinski, Volnei Antonio Pedroni, Alexandre de Almeida Prado Pohl

Proceedings of the IEEE International Symposium on Broadband Multimedia Systems and Broadcasting, 2016

2015

The energy cost of network security: A hardware vs. software comparison.

André Luiz Pereira de França, Ricardo P. Jasinski, Paulo Cemin, Volnei A. Pedroni, Altair Olivo Santin

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Moving Network Protection from Software to Hardware: An Energy Efficiency Analysis.

André Luiz Pereira de França, Ricardo Pereira Jasinski, Volnei Antonio Pedroni, Altair Olivo Santin

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2012

A new hardware coprocessor for accelerating Notification-Oriented applications.

Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean M. Simao

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011

A very efficient single-iteration oldest-out data sorter.

Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Jari Nurmi: Processor Design - System-on-Chip Computing for ASICs and FPGAs. Springer (2007) ISBN 978-1-4020-5529-4.

Ricardo P. Jasinski

Comput. J., 2010

An Improved GF(2) Matrix Inverter with Linear Time Complexity.

Ricardo P. Jasinski, Volnei A. Pedroni, Antonio Gortan, Walter Godoy Jr.

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart.

Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors.

Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Achieving near-MLD performance with soft information-set decoders implemented in FPGAs.

Antonio Gortan, Ricardo P. Jasinski, Walter Godoy Jr., Volnei A. Pedroni

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2007

Fault-Tolerance Techniques for SRAM-Based FPGAs.

Ricardo P. Jasinski

Comput. J., 2007

2004

Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs.

Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004