Richard F. Hobson

According to our database, Richard F. Hobson authored at least 22 papers between 1976 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2015

A framework for high-speed parallel-prefix adder performance evaluation and comparison.

Richard F. Hobson

Int. J. Circuit Theory Appl., 2015

2010

Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC.

Hooman Jarollahi, Richard F. Hobson

Proceedings of the 2010 International Conference on Computer Design, 2010

A Low-Power, Pulsed Domino CMOS 64-bit Adder.

Richard F. Hobson

Proceedings of the 2010 International Conference on Computer Design, 2010

2009

A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist.

Richard F. Hobson

Proceedings of the 2009 International Conference on Computer Design, 2009

2007

A New Single-Ended SRAM Cell With Write-Assist.

Richard F. Hobson

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

Signal Processing with Teams of Embedded Workhorse Processors.

Richard F. Hobson, Allan R. Dyck, Keith L. Cheung, Bill Ressl

EURASIP J. Embed. Syst., 2006

2005

An Area-Efficient High-Speed AES S-Box Method.

Richard F. Hobson, Scott Wakelin

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004

SoC Features for a Multi-Processor WCDMA Base-station Modem.

Richard F. Hobson, Allan R. Dyck, Keith L. Cheung

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

1999

A parallel embedded-processor architecture for ATM reassembly.

Richard F. Hobson, P. S. Wong

IEEE/ACM Trans. Netw., 1999

User selectable feature support for an embedded processor.

Allan R. Dyck, Scott Evenson, Henry Fu, Richard F. Hobson

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A Multiple-Input Single-Phase Clock Flip-Flop Family.

Richard F. Hobson, Allan R. Dyck

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Greedy Router with Technology Targetable Output.

R. Balakrishnan, Richard F. Hobson

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Power Reducing Techniques for Clocked CMOS PLAs.

Richard F. Hobson

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1995

An efficient maximum-redundancy radix-8 SRT division and square-root method.

Richard F. Hobson, Michael W. Fraser

IEEE J. Solid State Circuits, January, 1995

1989

Opportunities for System and User Features in a New APL Interpreter.

Richard F. Hobson, J. D. Hoskin, R. W. Spilsbury

Proceedings of the Conference Proceedings on APL as a Tool of Thought, 1989

1988

Multiprocessor experiments for high-speed ray tracing.

Severin Gaudet, Richard F. Hobson, Pradeep Chilka, Thomas W. Calvert

ACM Trans. Graph., 1988

1984

A Directly Executable Encoding for APL.

Richard F. Hobson

ACM Trans. Program. Lang. Syst., 1984

1981

High-level microprogramming with APL syntax.

Richard F. Hobson, Patrick Hannon, Jonathan Thornburg

Proceedings of the 14th annual workshop on Microprogramming, 1981

Structured Machine Design: An Ongoing Experiement.

Richard F. Hobson

Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

Software sympathetic chip set design.

Richard F. Hobson

Proceedings of the American Federation of Information Processing Societies: 1981 National Computer Conference, 1981

1978

Computing science hardware laboratories and the LSI revolution.

Richard F. Hobson

Proceedings of the Papers of the SIGCSE/CSA technical symposium on Computer science education, 1978

1976

GPMS, a general purpose memory management system - user's memory - that is.

I. Ganapathy, Richard F. Hobson

Proceedings of the eighth international conference on APL, 1976