Hooman Jarollahi

According to our database1, Hooman Jarollahi authored at least 12 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2016
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2015
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks.
J. Signal Process. Syst., 2014

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Associative Memories Based on Multiple-Valued Sparse Clustered Networks.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

2013
Reduced-complexity binary-weight-coded associative memories.
Proceedings of the IEEE International Conference on Acoustics, 2013

Selective decoding in associative memories based on Sparse-Clustered Networks.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

A low-power Content-Addressable Memory based on clustered-sparse networks.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Architecture and implementation of an associative memory using sparse clustered networks.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010
Dynamic Power Reduction in a Novel CMOS 5T-SRAM for Low-Power SoC.
Proceedings of the 2010 International Conference on Computer Design, 2010


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