Richard M. Sedmak

According to our database1, Richard M. Sedmak authored at least 7 papers between 1980 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2001
Unsafe board states during PC-based boundary-scan testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1996
Spanning the Product Life Cycle: RASSP DFT.
IEEE Des. Test Comput., 1996

1995
A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP).
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1986
On the Possible Limits of External Testing.
Proceedings of the Proceedings International Test Conference 1986, 1986

1984
Probing the State of the Art.
IEEE Des. Test, 1984

1982
Self-Test Chip to System Level Approaches.
Proceedings of the Proceedings International Test Conference 1982, 1982

1980
Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration.
IEEE Trans. Computers, 1980


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