Bill Eklow

According to our database1, Bill Eklow authored at least 39 papers between 1994 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2012, "For leadership in test technology for printed circuit assemblies and systems".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Recap of the ITC15 Test Conference.
IEEE Des. Test, 2016

2015
No Fault Found: The root cause.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2014
Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Protecting against emerging vmin failures in advanced technology nodes.
Proceedings of the 2014 International Test Conference, 2014

A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs.
Proceedings of the 2014 International Test Conference, 2014

An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
On Effective Through-Silicon Via Repair for 3-D-Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On effective and efficient in-field TSV repair for stacked 3D ICs.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Managing Complex Boundary-Scan Operations.
IEEE Des. Test Comput., 2012

FALCON: Rapid statistical fault coverage estimation for complex designs.
Proceedings of the 2012 IEEE International Test Conference, 2012

Re-using chip level DFT at board level.
Proceedings of the 17th IEEE European Test Symposium, 2012

On effective TSV repair for 3D-stacked ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Yield enhancement for 3D-stacked ICs: Recent advances and challenges.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Major Milestones for Two IEEE Standards Groups in 2011.
IEEE Des. Test Comput., 2011

2009
An Incremental Approach to Functional Diagnosis.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Embedded Testing in an In-Circuit Test Environment.
Proceedings of the 2008 IEEE International Test Conference, 2008

Parametric Testing of Optical Interfaces.
Proceedings of the 2008 IEEE International Test Conference, 2008

2006
Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics.
Proceedings of the 2006 IEEE International Test Conference, 2006

IEEE P1687: Toward Standardized Access of Embedded Instrumentation.
Proceedings of the 2006 IEEE International Test Conference, 2006

New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG).
Proceedings of the 11th European Test Symposium, 2006

2005
IJTAG (internal JTAG): a step toward a DFT standard.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Optimized reasoning-based diagnosis for non-random, board-level, production defects.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

An update on IEEE 1149.6 - successes and issues.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A practical perspective on reducing ASIC NTFs.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
"Real Life" System Testing of Networking Equipment.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Realizing High Test Quality Goals with Smart Test Resource Usage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Simulation Based System Level Fault Insertion Using Co-verification Tools.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

What Do You Mean My Board Test Stinks?
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Status of IEEE Testability Standards 1149.4, 1532 and 1149.6.
Proceedings of the 2004 Design, 2004

IP Testing - The Future Differentiator?
Proceedings of the 2004 Design, 2004

2003
IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks.
IEEE Des. Test Comput., 2003

IEEE 1149.6 - A Practical Perspective.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Is Board Test Worth Talking About?
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Unsafe board states during PC-based boundary-scan testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1998
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1994
Optimizing Boundary Scan in a Proprietary Environment.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994


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