Jean-Philippe Diguet

According to our database1, Jean-Philippe Diguet authored at least 154 papers between 1996 and 2019.

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2019
A novel Xilinx-based architecture for 3D-graphics.
Multimedia Tools Appl., 2019

Reinforcement-Learning Approach Guidelines for Energy Management.
J. Low Power Electronics, 2019

Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems.
JETC, 2019

CDMA-based multiple multicast communications on WiNOC for efficient parallel computing.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Risk assessment of SDR-based attacks with UAVs.
Proceedings of the 16th International Symposium on Wireless Communication Systems, 2019

A Case Study of Primary User Arrival Prediction Using the Energy Detector and the Hidden Markov Model in Cognitive Radio Networks.
Proceedings of the 2019 IEEE Symposium on Computers and Communications, 2019

Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Crossbar Memory Architecture Performing Memristor Overwrite Logic.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

MRL Crossbar-Based Full Adder Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Integrating Operators' Preferences into Decisions of Unmanned Aerial Vehicles: Multi-layer Decision Engine and Incremental Preference Elicitation.
Proceedings of the Algorithmic Decision Theory - 6th International Conference, 2019

2018
Networked Power-Gated MRAMs for Memory-Based Computing.
IEEE Trans. VLSI Syst., 2018

Context/Resource-Aware Mission Planning Based on BNs and Concurrent MDPs for Autonomous UAVs.
Sensors, 2018

Towards Dynamically Reconfigurable SoCs (DRSoCs) in industrial automation: State of the art, challenges and opportunities.
Microprocess. Microsystems, 2018

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip.
J. Parallel Distributed Comput., 2018

Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Accurate Channel Models for Realistic Design Space Exploration of Future Wireless NoCs.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Autonomic Management of Reconfigurations in DPR FPGA-based Embedded System.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

BFM: a Scalable and Resource-Aware Method for Adaptive Mission Planning of UAVs.
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

Security aspects of neuromorphic MPSoCs.
Proceedings of the International Conference on Computer-Aided Design, 2018

A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures.
Proceedings of the 2018 IEEE International Conference on Autonomic Computing, 2018

Model-Based Dependability Analysis of Unmanned Aerial Vehicles - A Case Study.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018

Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications.
Proceedings of the 55th Annual Design Automation Conference, 2018

Discrete and Logico-Numerical Control for Dynamic Partial Reconfigurable FPGA-Based Embedded Systems: A Case Study.
Proceedings of the IEEE Conference on Control Technology and Applications, 2018

2017
Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs.
Signal Processing Systems, 2017

DTFM: a flexible model for schedulability analysis of real-time applications on NoC-based architectures.
SIGBED Review, 2017

Embedded context aware diagnosis for a UAV SoC platform.
Microprocess. Microsystems, 2017

Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform.
Int. J. Reconfig. Comp., 2017

Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding.
EURASIP J. Adv. Sig. Proc., 2017

Exploring the performance of partially reconfigurable point-to-point interconnects.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

NoC-MRAM architecture for memory-based computing: Database-search case study.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Modeling and Validation of a Mixed-Criticality NoC Router Using the IF Language.
Proceedings of the 10th International Workshop on Network on Chip Architectures, 2017

Hardware Acceleration of the Tracking Learning Detection (TLD) Algorithm on FPGA.
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017

DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Autonomic management of missions and reconfigurations in FPGA-based embedded system.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding.
IEEE Trans. VLSI Syst., 2016

TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA.
ACM Trans. Embedded Comput. Syst., 2016

Model-Based Design of Correct Controllers for Dynamically Reconfigurable Architectures.
ACM Trans. Embedded Comput. Syst., 2016

Dynamic NoC buffer allocation for MPSoC timing side channel attack protection.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Task Clustering Approach to Optimize the Scheduling on a Partially Dynamically Reconfigurable FPGAs for image processing algorithms.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Notifying memories: a case-study on data-flow applications with NoC interfaces implementation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst., 2015

NoC-Based Protection for SoC Time-Driven Attacks.
Embedded Systems Letters, 2015

Dedicated object processor for mobile augmented reality - sailor assistance case study.
EURASIP J. Emb. Sys., 2015

TSV protection: Towards secure 3D-MPSoC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Radio signature based posture recognition using WBSN.
Proceedings of the 14th International Conference on Information Processing in Sensor Networks, 2015

FPGA implementation of Bayesian network inference for an embedded diagnosis.
Proceedings of the 2015 IEEE Conference on Prognostics and Health Management, 2015

Discrete Control-Based Design of Adaptive and Autonomic Computing Systems.
Proceedings of the Distributed Computing and Internet Technology, 2015

Embedded real-time localization of UAV based on an hybrid device.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Low-complexity energy proportional posture/gesture recognition based on WBSN.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

Bayesian network-based framework for the design of reconfigurable health management monitors.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling.
TRETS, 2014

Hardware adaptation for multimedia application case study: Augmented reality.
Proceedings of the 6th International Conference of Soft Computing and Pattern Recognition, 2014

Self-Adaptive Network On Chips.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

3D-LeukoNoC: A dynamic NoC protection.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Extensible Global Model Management with Meta-model Subsets and Model Synchronization.
Proceedings of the 2nd International Workshop on The Globalization of Modeling Languages co-located with ACM/IEEE 17th International Conference on Model Driven Engineering Languages and Systems, 2014

Synchronization of Models of Rich Languages with Triple Graph Grammars: An Experience Report.
Proceedings of the Theory and Practice of Model Transformations, 2014

Elastic security zones for NoC-based 3D-MPSoCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Mobile Augmented Reality System for Marine Navigation Assistance.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Virtual Devices for Hot-Pluggable Processors.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Orcc's compa-backend demonstration.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoC.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

2013
Configurable memory security in embedded systems.
ACM Trans. Embedded Comput. Syst., 2013

Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach.
Int. J. Reconfig. Comp., 2013

Self-Adaptive Network-on-Chip Interface.
Embedded Systems Letters, 2013

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Embedded System Architecture for Mobile Augmented Reality - Sailor Assistance Case Study.
Proceedings of the PECCS 2013, 2013

SNet, a flexible, scalable network paradigm for manycore architectures.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Virtual UARTs for Reconfigurable Multi-processor Architectures.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Autonomic Management of Dynamically Partially Reconfigurable FPGA Architectures Using Discrete Control.
Proceedings of the 10th International Conference on Autonomic Computing, 2013

Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Scalable NoC-based architecture of neural coding for new efficient associative memories.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance.
TRETS, 2012

A contribution to the reduction of the dynamic power dissipation in the turbo decoder.
Annales des Télécommunications, 2012

Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Designing formal reconfiguration control using UML/MARTE.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Hardware accelerator for self adaptive augmented reality systems.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

MHPM: Multi-Scale Hybrid Programming Model: A Flexible Parallelization Methodology.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

A framework for high-level synthesis of heterogeneous MP-SoC.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Modeling and synthesis of a Dynamic and Partial Reconfiguration controller.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Lightweight reconfiguration security services for AXI-based MPSoCs.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Bus-based MPSoC Security through Communication Protection: A Latency-efficient Alternative.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Closed-loop-based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study.
ACM Trans. Embedded Comput. Syst., 2011

Asymmetric cache coherency: Improving multicore performance for non-uniform workloads.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Distributed Security for Communications and Memories in a Multiprocessor Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Dynamic routing strategy for embedded distributed architectures.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Efficient key-dependent message authentication in reconfigurable hardware.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Modeling and Formal Control of Partial Dynamic Reconfiguration.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

MPSoC Architecture-Aware Automatic NoC Topology Design.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2010

Predictibility of inter-component latency in a software communications architecture operating environment.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

XPSoC: A reconfigurable solution for multimedia contents protection.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Rapid Application Development on Multi-processor Reconfigurable Systems.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Self-reconfigurable Embedded Systems: From Modeling to Implementation.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

UML design for dynamically reconfigurable multiprocessor embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A security approach for off-chip memory in embedded microprocessor systems.
Microprocess. Microsystems, 2009

Energy and Power Consumption Estimation for Embedded Applications and Operating Systems.
J. Low Power Electronics, 2009

Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Model Driven High-Level Power Estimation of Embedded Operating Systems Communication Services.
Proceedings of the International Conference on Embedded Software and Systems, 2009

Networked Self-adaptive Systems: An Opportunity for Configuring in the Large.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

A co-design approach for embedded system modeling and code generation with UML and MARTE.
Proceedings of the Design, Automation and Test in Europe, 2009

Proactive remote healthcare based on multimedia and home automation services.
Proceedings of the IEEE Conference on Automation Science and Engineering, 2009

Ultra-Fast Downloading of Partial Bitstreams through Ethernet.
Proceedings of the Architecture of Computing Systems, 2009

2008
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective.
IEEE Trans. VLSI Syst., 2008

Reconfiguration Management in the Context of RTOS-Based HW/SW Embedded Systems.
EURASIP J. Emb. Sys., 2008

A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis.
EURASIP J. Emb. Sys., 2008

Key Research Issues for Reconfigurable Network-on-Chip.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

Memory security management for reconfigurable embedded systems.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Refining Power Consumption Estimations in the Component-based AADL Design Flow.
Proceedings of the Forum on specification and Design Languages, 2008

Power and Energy Estimations in Model-Based Design.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

Specification and OS-based implementation of self-adaptive, hardware/software embedded systems.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

A Networked, Lightweight and Partially Reconfigurable Platform.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Energy Efficient Turbo Decoder with Reduced State Metric Quantization.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A Code Compression Method to Cope with Security Hardware Overheads.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

NOC-centric Security of Reconfigurable SoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Efficient space-time noc path allocation based on mutual exclusion and pre-reservation.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Confiuartion Management in the Context of Self Adapative Systems.
Proceedings of the FPL 2007, 2007

High-efficiency protection solution for off-chip memory in embedded systems.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A Code Compression Method with Confidentiality and Integrity Checking.
Proceedings of the 2007 International Conference on Embedded Systems & Applications, 2007

2006
Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter.
VLSI Signal Processing, 2006

RTDT: A static QoS manager, RT scheduling, HW/SW partitioning CAD tool.
Microelectron. J., 2006

EPICURE: A partitioning and co-design framework for reconfigurable computing.
Microprocessors and Microsystems, 2006

NoC Design Flow for TDMA and QoS Management in a GALS Context.
EURASIP J. Emb. Sys., 2006

Design of multimedia processor based on metric computation
CoRR, 2006

Automated derivation of NoC Communication Specifications from Application Constraints.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

System Level Design with UML: a Unified Approach.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Secure Architecture in Embedded Systems: an Overview.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

RTOS extensions for dynamic hardware / software monitoring and configuration management.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Trusted computing - A new challenge for embedded systems.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

2005
Processor Enhancements for Media Streaming Applications.
VLSI Signal Processing, 2005

Design-Trotter: System-level dynamic estimation task a first step towards platform architecture selection.
J. Embedded Computing, 2005

Design of a multimedia processor based on metrics computation.
Adv. Eng. Softw., 2005

Feedback control modelling for learning reconfigurable embedded systems.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

2004
High performance architecture of integrated protocols for encoded video application.
Comput. Stand. Interfaces, 2004

2003
Estimation du parallélisme au niveau système pour l'exploration de l'espace de conception de systèmes enfouis.
Technique et Science Informatiques, 2003

Multi-Granularity Metrics for the Era of Strongly Personalized SOCs.
Proceedings of the 2003 Design, 2003

2002
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Design-Trotter: a multimedia embedded systems design space exploration tool.
Proceedings of the IEEE 5th Workshop on Multimedia Signal Processing, 2002

2001
A Flow Control Approach for Encoded Video Applications Over ATM Network.
Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 2001

2000
A Framework for High Level Estimations of Signal Processing VLSI Implementations.
VLSI Signal Processing, 2000

1998
Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings.
IEEE Trans. VLSI Syst., 1998

How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Formalized methodology for data reuse exploration in hierarchical memory mappings.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1996
Memory aspects in signal processing and HLS tool: Some results.
Proceedings of the 8th European Signal Processing Conference, 1996


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