Robert J. Halstead

Affiliations:
  • University of California, Riverside, CA, USA (PhD 2015)


According to our database1, Robert J. Halstead authored at least 13 papers between 2010 and 2021.

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Bibliography

2021
Efficient local locking for massively multithreaded in-memory hash-based operators.
VLDB J., 2021

2016
FPGA-accelerated group-by aggregation using synchronizing caches.
Proceedings of the 12th International Workshop on Data Management on New Hardware, 2016

ROCCC 2.0.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Using Multithreaded Techniques to Mask Memory Latency on FPGA Accelerators.
PhD thesis, 2015

High-Level Language Tools for Reconfigurable Computing.
Proc. IEEE, 2015

FPGA-based Multithreading for In-Memory Hash Joins.
Proceedings of the Seventh Biennial Conference on Innovative Data Systems Research, 2015

2014
A study on parallelizing XML path filtering using accelerators.
ACM Trans. Embed. Comput. Syst., 2014

Compiling irregular applications for reconfigurable systems.
Int. J. High Perform. Comput. Netw., 2014

2013
Accelerating Join Operation for Relational Databases with FPGAs.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Compiled multithreaded data paths on FPGAs for dynamic workloads.
Proceedings of the International Conference on Compilers, 2013

2011
Efficient XML Path Filtering Using GPUs.
Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2011

Exploring irregular memory accesses on FPGAs.
Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

2010
Designing Modular Hardware Accelerators in C with ROCCC 2.0.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010


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