Prerna Budhkar

According to our database, Prerna Budhkar authored at least 14 papers between 2015 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations.

Srivatsa Rangachar Srinivasa, Dileep John Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Mikhail J. Moiseev, Robert J. Munoz, Anuradha Srinivasan, Tanay Karnik

IEEE J. Solid State Circuits, January, 2026

2025

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations.

Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Arun Radhakrishnan, Alejandro Cardenas Lopez, Jainaveen Sundaram, Vinayak Honkote, Leonid Azarenkov, Dan Lake, Jaykant Timbadiya, Mikhail J. Moiseev, Brando Perez Esparza, Ronald Kalim, Erika Ramirez Lozano, Mukesh Bhartiya, Sriram Muthukumar, Satish Yada, Sureshbabu Kadavakollu, Saransh Chhabra, Kamakhya Prasad Sahu, James Greensky, Xavier Brun, Esdras Juarez Hernandez, Robert Munoz, Thomas P. Thomas, Shawna Liff, Vivek De, Anuradha Srinivasan, Tanay Karnik

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration.

Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution.

Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Jaykant Timbadiya, Satish Yada, Suresh Kadavakollu, James Greensky, Gauthaman Murali, Anuradha Srinivasan, Ragh Kuttappa, Tanay Karnik

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

A 68 TOPS/W, 256MB SRAM Sparse GEMM Accelerator Tiled Across 16, 4nm Near Memory Compute (NMC) Chiplets Disaggregated 2.5D System.

Srivatsa Rangachar Srinivasa, Prerna Budhkar, Gauthaman Murali, Vui Seng Chua, Paolo A. Aseron, Vinayak Honkote, Ravi R. Iyer, Nilesh Jain, Dileep John Kurian, Anuradha Srinivasan, Tanay Karnik

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A High-Performance Passive Base System for Distributed AI/Media Acceleration.

Ragh Kuttappa, Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Paolo A. Aseron, Gauthaman Murali, Vinayak Honkote, Prerna Budhkar, Dileep Kurian, Ronald Kalim, Thomas P. Thomas, Anuradha Srinivasan, Tanay Karnik

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2023

CPU Microarchitectural Performance Analysis of SVT-AV1 Encoder.

Prerna Budhkar, Navneet Rao, Jainaveen Sundaram, Tanay Karnik

Proceedings of the IEEE International Conference on Image Processing, 2023

2021

Efficient local locking for massively multithreaded in-memory hash-based operators.

Bashar Romanous, Skyler Windh, Ildar Absalyamov, Prerna Budhkar, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras

VLDB J., 2021

2019

Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads.

Prerna Budhkar, Ildar Absalyamov, Vasileios Zois, Skyler Windh, Walid A. Najjar, Vassilis J. Tsotras

ACM Trans. Archit. Code Optim., 2019

Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs.

Eriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Accelerating Irregular Applications Using Latency Masking Multithreaded Techniques.

Prerna Budhkar

PhD thesis, 2018

2016

FPGA-accelerated group-by aggregation using synchronizing caches.

Ildar Absalyamov, Prerna Budhkar, Skyler Windh, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras

Proceedings of the 12th International Workshop on Data Management on New Hardware, 2016

2015

High-Level Language Tools for Reconfigurable Computing.

Skyler Windh, Xiaoyin Ma, Robert J. Halstead, Prerna Budhkar, Zabdiel Luna, Omar Hussaini, Walid A. Najjar

Proc. IEEE, 2015

CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAs.

Skyler Windh, Prerna Budhkar, Walid A. Najjar

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015