Bharat Sukhwani

Orcid: 0000-0002-3703-2554

According to our database1, Bharat Sukhwani authored at least 23 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design.
Proceedings of the 29th Symposium on Operating Systems Principles, 2023

Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

A Hardware/Software Approach for Database Query Acceleration with FPGAs.
Int. J. Parallel Program., 2015

Database Analytics: A Reconfigurable-Computing Approach.
IEEE Micro, 2014

Increasing Parallelism and Reducing Thread Contentions in Mapping Localized N-Body Simulations to GPUs.
Proceedings of the Numerical Computations with GPUs, 2014

Large Payload Streaming Database Sort and Projection on FPGAs.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

FINPAGE: Generating high performance feed-specific parser circuits.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

Accelerating Join Operation for Relational Databases with FPGAs.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Database analytics acceleration using FPGAs.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

High-Throughput, Lossless Data Compresion on FPGAs.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

FPGA acceleration of rigid-molecule docking codes.
IET Comput. Digit. Tech., 2010

Fast binding site mapping using GPUs and CUDA.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

FPGA-based acceleration of CHARMM-potential minimization.
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, 2009

GPU acceleration of a production molecular docking code.
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, 2009

Computing Models for FPGA-Based Accelerators.
Comput. Sci. Eng., 2008

Extensible On-Chip Peripherals.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008

Acceleration of a production rigid molecule docking code.
Proceedings of the FPL 2008, 2008

An Extensible I/O Subsystem.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Simulation and Design of Nanocircuits With Resonant Tunneling Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Single pass streaming BLAST on FPGAs.
Parallel Comput., 2007

Achieving High Performance with FPGA-Based Computing.
Computer, 2007

Single Pass, BLAST-Like, Approximate String Matching on FPGAs.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006