Rodrigo Travessini

According to our database1, Rodrigo Travessini authored at least 4 papers between 2018 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy.
J. Electron. Test., 2019

2018
A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs.
Microelectron. Reliab., 2018

Processor checkpoint recovery for transient faults in critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Processor core profiling for SEU effect analysis.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018


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