Paulo Ricardo Cechelero Villa

According to our database, Paulo Ricardo Cechelero Villa authored at least 9 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy.

Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Roger C. Goerl, Fabian Luis Vargas, Eduardo Augusto Bezerra

J. Electron. Test., 2019

A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture.

Estevan Lara, Guilherme Debon, Roger C. Goerl, Paulo Ricardo Cechelero Villa, Dorian Schramm, Leticia B. Poehls, Fabian Vargas

Proceedings of the IEEE Latin American Test Symposium, 2019

2018

A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs.

Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Marcelo Daniel Berejuck, Eduardo Augusto Bezerra

Microelectron. Reliab., 2018

An efficient EDAC approach for handling multiple bit upsets in memory array.

Roger C. Goerl, Paulo Ricardo Cechelero Villa, Letícia Maria Veiras Bolzani, Eduardo Augusto Bezerra, Fabian Luis Vargas

Microelectron. Reliab., 2018

Processor checkpoint recovery for transient faults in critical applications.

Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Fabian Luis Vargas, Eduardo Augusto Bezerra

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Processor core profiling for SEU effect analysis.

Rodrigo Travessini, Paulo Ricardo Cechelero Villa, Fabian Luis Vargas, Eduardo Augusto Bezerra

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017

Analysis of single-event upsets in a Microsemi ProAsic3E FPGA.

Paulo Ricardo Cechelero Villa, Roger C. Goerl, Fabian Vargas, Leticia B. Poehls, Nilberto H. Medina, Nemitala Added, Vitor A. P. de Aguiar, Eduardo L. A. Macchione, Fernando Aguirre, Marcilei Aparecida Guazzelli da Silveira, Eduardo Augusto Bezerra

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2015

A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow.

Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Horácio C. Neto, Eduardo Augusto Bezerra

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A reconfigurable hardware platform for power converter control systems.

Paulo Ricardo Cechelero Villa, Eduardo Augusto Bezerra, Djones Vinicius Lettnin, Samir A. Mussa

Proceedings of the IEEE International Conference on Industrial Technology, 2015