Ronglong Wu

Orcid: 0009-0001-9008-5401

According to our database1, Ronglong Wu authored at least 8 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
From In-Place Updates to Out-of-Place Selections: Reconsidering Write Disturbance in Non-Volatile Memory.
ACM Trans. Storage, February, 2026

Predicting DRAM Failures at Scale: A Two-Stage Approach for Heterogeneous Systems.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

2025
MetoHash: A Memory-Efficient and Traffic-Optimized Hashing Index on Hybrid PMem-DRAM Memories.
Proceedings of the International Conference for High Performance Computing, 2025

AC-Cache: A Memory-Efficient Caching System for Small Objects via Exploiting Access Correlations.
Proceedings of the 30th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, 2025

DraEC: A Decentralized Routing Algorithm in Erasure-Coded Deduplication System.
Proceedings of the Advanced Parallel Processing Technologies, 2025

2024
Relieving Write Disturbance for Phase Change Memory With RESET-Aware Data Encoding.
IEEE Trans. Computers, August, 2024

Removing Obstacles before Breaking Through the Memory Wall: A Close Look at HBM Errors in the Field.
Proceedings of the 2024 USENIX Annual Technical Conference, 2024

Mitigating Write Disturbance in Non-Volatile Memory via Coupling Machine Learning with Out-of-Place Updates.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024


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