Ronny Krashinsky

According to our database1, Ronny Krashinsky authored at least 10 papers between 2001 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Convergence and scalarization for data-parallel architectures.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012
Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2008
Implementing the scale vector-thread processor.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
Vector-thread architecture and implementation.
PhD thesis, 2007

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.
IEEE Trans. VLSI Syst., 2007

2005
Minimizing Energy for Wireless Web Access with Bounded Slowdown.
Wireless Networks, 2005

2004
The Vector-Thread Architecture.
IEEE Micro, 2004

Cache Refill/Access Decoupling for Vector Machines.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

2001
Multithreading decoupled architectures for complexity-effective general purpose computing.
SIGARCH Computer Architecture News, 2001


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