Roope Kaivola

According to our database1, Roope Kaivola authored at least 21 papers between 1991 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2013
Relational STE and theorem proving for formal verification of industrial circuit designs.
Proceedings of the Formal Methods in Computer-Aided Design, 2013

2011
Intel Core<sup>TM</sup> i7 Processor Execution Engine Validation in a Functional Language Based Formal Framework.
Proceedings of the Practical Aspects of Declarative Languages, 2011

2009
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2005
Stepwise Development of Process-Algebraic Specifications in Decorated Trace Semantics.
Formal Methods Syst. Des., 2005

Formal verification of high-level conformance with symbolic simulation.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants.
Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2003
Proof engineering in the large: formal verification of Pentium?4 floating-point divider.
Int. J. Softw. Tools Technol. Transf., 2003

2002
Formal Verification of the Pentium ® 4 Floating-Point Multiplier.
Proceedings of the 2002 Design, 2002

2001
Formal verification of the Pentium<sup>(R)</sup> 4 multiplier.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Proof Engineering in the Large: Formal Verification of Pentium<sup>®</sup> 4 Floating-Point Divider.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
Divider Circuit Verification with Model Checking and Theorem Proving.
Proceedings of the Theorem Proving in Higher Order Logics, 13th International Conference, 2000

Formal verification of iterative algorithms in microprocessors.
Proceedings of the 37th Conference on Design Automation, 2000

1998
Axiomatising Extended Computation Tree Logic.
Theor. Comput. Sci., 1998

1997
Using Compositional Preorders in the Verification of Sliding Window Protocal.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997

1996
Fixpoints for Rabin Tree Automata Make Complementation Easy.
Proceedings of the Automata, Languages and Programming, 23rd International Colloquium, 1996

1995
On Modal mu-Calculus and Büchi Tree Automata.
Inf. Process. Lett., 1995

A Simple Decision Method for the Linear Time Mu-calculus.
Proceedings of the International Workshop on Structures in Concurrency Theory, 1995

Axiomatising Linear Time Mu-calculus.
Proceedings of the CONCUR '95: Concurrency Theory, 1995

1992
The Weakest Compositional Semantic Equivalence Preserving Nexttime-less Linear temporal Logic.
Proceedings of the CONCUR '92, 1992

Compositional Model Checking for Linear-Time Temporal Logic.
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991
Using Truth-Preserving Reductions to Improve the Clarity of Kripke-Models.
Proceedings of the CONCUR '91, 1991


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