Rajnish Ghughal

According to our database1, Rajnish Ghughal authored at least 8 papers between 1997 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2014
Formally Verifying Graphics FPU - An Intel® Experience.
Proceedings of the FM 2014: Formal Methods, 2014

2012
Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

2009
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2001
Applications of Hierarchical Verification in Model Checking.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
Verification Methods for Weaker Shared Memory Consistency Models.
Proceedings of the Parallel and Distributed Processing, 2000

1998
Using "Test Model-Checking" to Verify the Runway-PA8000 Memory Model.
Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, 1998

The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997
Formal modeling and validation applied to a commercial coherent bus: a case study.
Proceedings of the Advances in Hardware Design and Verification, 1997


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