Naren Narasimhan

According to our database1, Naren Narasimhan authored at least 9 papers between 1996 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2009
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2004
Reference model based RTL verification: an integrated approach.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2002
Formal Verification of the Pentium ® 4 Floating-Point Multiplier.
Proceedings of the 2002 Design, 2002

2001
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis.
Formal Methods Syst. Des., 2001

Formal verification of the Pentium<sup>(R)</sup> 4 multiplier.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

1998
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System.
Proceedings of the Theorem Proving in Higher Order Logics, 11th International Conference, 1998

1996
Synchronous Controller Models for Synthesis from Communicating VHDL Processes.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Specification of Control Flow Properties for Verification of Synthesized VHDL Designs.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Rapid Prototyping of Reconfigurable Coprocessors.
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996


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