Rui Li

Orcid: 0000-0002-2953-9742

Affiliations:
  • ShanghaiTech University, School of Information Science and Technology, China


According to our database1, Rui Li authored at least 7 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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Bibliography

2025
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

2023
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2021
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
An Accurate FPGA Online Delay Monitor Supporting All Timing Paths.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020


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