Yuhao Shu

Orcid: 0000-0002-0357-4507

According to our database1, Yuhao Shu authored at least 21 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Design of an Aging-Aware Memory With BTI-Mitigated SA and System-Visible Lifetime Management.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026

DSHD-CAM: High-Throughput RRAM CAM Leveraging Dynamic Shifted Hamming Distance for Genome Analysis.
IEEE Trans. Very Large Scale Integr. Syst., May, 2026

M<sup>3</sup>CAM: An MLC RRAM-Based Multi-Bit CAM Design Supporting In-Memory Operation of Multi-State Hamming Distance.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

ACIMC: A 342.7-TOPS/mm<sup>2</sup> eDRAM-Based Analog Cryogenic In-Memory Computing Macro.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2026

A Complementary 3T-Based eDRAM Macro for High-Density Dual-Direction CAM and Logic-in-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2026

2025
An Energy-Efficient and Real-Time FPGA-Based Point Cloud Registration Framework with Ultra-Fast and Configurable Multi-Mode Correspondence Search.
ACM Trans. Reconfigurable Technol. Syst., December, 2025

A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory.
IEEE Trans. Very Large Scale Integr. Syst., September, 2025

RSQC: Recursive Sparse QUBO Construction for Quantum Annealing Machines.
IEEE Trans. Computers, June, 2025

2024
eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations.
IEEE J. Solid State Circuits, November, 2024

EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications.
CoRR, 2023

RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations.
IEEE Trans. Very Large Scale Integr. Syst., 2022

2021
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles.
IEEE Trans. Circuits Syst. II Express Briefs, 2021


  Loading...