Yajun Ha
Orcid: 0000-0003-4244-5916
According to our database1,
Yajun Ha
authored at least 147 papers
between 1999 and 2024.
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Bibliography
2024
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
2023
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V<sub>DD</sub> Assist and Bitline Leakage Compensation.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023
Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications.
CoRR, 2023
RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Guest Editorial Special Issue on the 2021 IEEE International Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Computers, 2021
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles.
ACM Trans. Embed. Comput. Syst., 2020
A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base".
IEEE Trans. Very Large Scale Integr. Syst., 2019
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base.
IEEE Trans. Very Large Scale Integr. Syst., 2019
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications.
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018
2017
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
J. Syst. Archit., 2017
Proceedings of the Computing Frontiers Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms.
IEEE Trans. Computers, 2015
Microprocess. Microsystems, 2015
Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints.
IET Biom., 2015
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Challenges and future trends for embedded security in electric vehicular communications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
A heterogeneous platform with GPU and FPGA for power efficient high performance computing.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems.
IEEE Trans. Computers, 2013
IET Biom., 2013
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
The architecture and placement algorithm for a uni-directional routing based 3D FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013
Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors.
Proceedings of the 16th IEEE International Conference on Computational Science and Engineering, 2013
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
SIGARCH Comput. Archit. News, 2012
A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only).
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012
2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array.
IEEE Trans. Biomed. Circuits Syst., 2010
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage.
IEEE J. Solid State Circuits, 2010
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee.
Proceedings of the International Conference on Field-Programmable Technology, 2010
Proceedings of the International Conference on Field-Programmable Technology, 2010
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
An optimized design for serial-parallel finite field multiplication over <i>GF</i>(2<sup><i>m</i></sup>) based on all-one polynomials.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.
ACM Trans. Design Autom. Electr. Syst., 2008
Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming.
IEEE Trans. Mob. Comput., 2008
Tighter WCET analysis of input dependent programs with classified-cache memory architecture.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the FPL 2008, 2008
Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA.
Proceedings of the FPL 2008, 2008
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.
Proceedings of the FPL 2008, 2008
Proceedings of the FPL 2008, 2008
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008
Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
V<sub>t</sub> balancing and device sizing towards high yield of sub-threshold static logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools.
Proceedings of the FPL 2007, 2007
Proceedings of the FPL 2007, 2007
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.
Proceedings of the 44th Design Automation Conference, 2007
2006
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11.
Int. J. Softw. Eng. Knowl. Eng., 2005
Int. J. Softw. Eng. Knowl. Eng., 2005
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005
2002
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
J. Supercomput., 2002
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware.
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), 2000
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999