Ruwan N. S. Ratnayake

According to our database1, Ruwan N. S. Ratnayake authored at least 4 papers between 2004 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2008
A High-Throughput Maximum a Posteriori Probability Detector.
IEEE J. Solid State Circuits, 2008

2007
Serial Sum-Product Architecture for Low-Density Parity-Check Codes.
Proceedings of the 16th International Conference on Computer Communications and Networks, 2007

A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders.
Proceedings of the Global Communications Conference, 2007

2004
Pipelined parallel architecture for high throughput MAP detectors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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