Gu-Yeon Wei
Orcid: 0000-0001-5730-9904
According to our database1,
Gu-Yeon Wei
authored at least 222 papers
between 1996 and 2024.
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Bibliography
2024
Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface.
ACM Trans. Design Autom. Electr. Syst., March, 2024
Guac: Energy-Aware and SSA-Based Generation of Coarse-Grained Merged Accelerators from LLVM-IR.
CoRR, 2024
Flash: A Hybrid Private Inference Protocol for Deep CNNs with High Accuracy and Low Latency on CPU.
CoRR, 2024
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
IEEE Des. Test, December, 2023
Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials.
Int. J. High Perform. Comput. Appl., July, 2023
ACM Trans. Embed. Comput. Syst., March, 2023
A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs.
IEEE J. Solid State Circuits, February, 2023
A Binary-Activation, Multi-Level Weight RNN and Training Algorithm for ADC-/DAC-Free and Noise-Resilient Processing-in-Memory Inference With eNVM.
IEEE Trans. Emerg. Top. Comput., 2023
Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration.
ACM Trans. Embed. Comput. Syst., 2023
Architectural CO<sub>2</sub> Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool.
IEEE Micro, 2023
MAD Max Beyond Single-Node: Enabling Large Machine Learning Model Acceleration on Distributed Systems.
CoRR, 2023
INT2.1: Towards Fine-Tunable Quantized Large Language Models with Error Correction through Low-Rank Adaptation.
CoRR, 2023
CoRR, 2023
Design Space Exploration and Optimization for Carbon-Efficient Extended Reality Systems.
CoRR, 2023
PerfSAGE: Generalized Inference Performance Predictor for Arbitrary Deep Learning Models on Edge Devices.
CoRR, 2023
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
S<sup>3</sup>: Increasing GPU Utilization during Generative Inference for Higher Throughput.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Is the Future Cold or Tall? Design Space Exploration of Cryogenic and 3D Embedded Cache Memory.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
Characterizing the Scalability of Graph Convolutional Networks on Intel<sup>®</sup> PIUMA.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023
VelociTI: An Architecture-level Performance Modeling Framework for Trapped Ion Quantum Computers.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the 2nd Workshop on Sustainable Computer Systems, 2023
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
IEEE Trans. Computers, 2022
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators.
IEEE J. Solid State Circuits, 2022
CoRR, 2022
CoRR, 2022
Tabula: Efficiently Computing Nonlinear Activation Functions for Secure Neural Network Inference.
CoRR, 2022
Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface.
CoRR, 2022
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration.
CoRR, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
ACT: designing sustainable computer systems with an architectural carbon modeling tool.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
CoopMC: Algorithm-Architecture Co-Optimization for Markov Chain Monte Carlo Accelerators.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
GoldenEye: A Platform for Evaluating Emerging Numerical Data Formats in DNN Accelerators.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A joint management middleware to improve training performance of deep recommendation systems with SSDs.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles.
CoRR, 2021
Quantifying and Maximizing the Benefits of Back-End Noise Adaption on Attention-Based Speech Recognition Models.
CoRR, 2021
Machine Learning-Based Automated Design Space Exploration for Autonomous Aerial Robots.
CoRR, 2021
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
RecPipe: Co-designing Models and Hardware to Jointly Optimize Recommendation Quality and Performance.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
9.8 A 25mm<sup>2</sup> SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Gradient Disaggregation: Breaking Privacy in Federated Learning by Reconstructing the User Participant Matrix.
Proceedings of the 38th International Conference on Machine Learning, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33<sup>rd</sup> Hot Chips Symposium - August 22-24, 2021.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
2020
ACM Trans. Archit. Code Optim., 2020
IEEE Micro, 2020
IEEE Micro, 2020
Cheetah: Optimizations and Methods for PrivacyPreserving Inference via Homomorphic Encryption.
CoRR, 2020
CoRR, 2020
The Sky Is Not the Limit: A Visual Performance Model for Cyber-Physical Co-Design in Autonomous Machines.
IEEE Comput. Archit. Lett., 2020
A 3mm<sup>2</sup> Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Systematic Methodology for Analysis of Deep Learning Hardware and Software Platforms.
Proceedings of Machine Learning and Systems 2020, 2020
A comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
DeepRecSys: A System for Optimizing End-To-End At-Scale Neural Recommendation Inference.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the IEEE International Symposium on Workload Characterization, 2020
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE Hot Chips 32 Symposium, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Structured Compression by Weight Encryption for Unstructured Pruning and Quantization.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
ACM Trans. Archit. Code Optim., 2019
MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge.
IEEE Micro, 2019
IEEE J. Solid State Circuits, 2019
A binary-activation, multi-level weight RNN and training algorithm for processing-in-memory inference with eNVM.
CoRR, 2019
AdaptivFloat: A Floating-point based Data Type for Resilient Deep Learning Inference.
CoRR, 2019
CoRR, 2019
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization.
IEEE Comput. Archit. Lett., 2019
A 16nm 25mm<sup>2</sup> SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE/ACM International Workshop on Programming and Performance Visualization Tools, 2019
MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications.
IEEE J. Solid State Circuits, 2018
Proceedings of the 6th International Conference on Learning Representations, 2018
A Wide Dynamic Range Sparse FC-DNN Processor with Multi-Cycle Banked SRAM Read and Adaptive Clocking in 16nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01756-8, 2017
A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Cognitive Computing Safety: The New Horizon for Reliability / The Design and Evolution of Deep Learning Workloads.
IEEE Micro, 2017
A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle.
IEEE J. Solid State Circuits, 2017
Automatically accelerating non-numerical programs by architecture-compiler co-design.
Commun. ACM, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
21.5 A 3-to-5V input 100Vpp output 57.7mW 0.42% THD+N highly integrated piezoelectric actuator driver.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Using dynamic dependence analysis to improve the quality of high-level synthesis designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications.
IEEE J. Solid State Circuits, 2016
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
2015
Proceedings of the Symposium on VLSI Circuits, 2015
A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter.
Proceedings of the Symposium on VLSI Circuits, 2015
Quantifying sources of error in McPAT and potential impacts on architectural studies.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Evaluating Adaptive Clocking for Supply-Noise Resilience in Battery-Powered Aerial Microrobotic System-on-Chip.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
IEEE Comput. Archit. Lett., 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Quantifying acceleration: Power/performance trade-offs of application kernels in hardware.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Supply-noise resilient adaptive clocking for battery-powered aerial microrobotic System-on-Chip in 40nm CMOS.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A fully integrated battery-connected switched-capacitor 4: 1 voltage regulator with 70% peak efficiency using bottom-plate charge recycling.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
ACM Trans. Archit. Code Optim., 2012
IEEE Micro, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the 2011 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2011
Achieving uniform performance and maximizing throughput in the presence of heterogeneity.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
ACM Trans. Archit. Code Optim., 2010
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity.
IEEE Micro, 2010
The Accelerator Store framework for high-performance, low-power accelerator-based systems.
IEEE Comput. Archit. Lett., 2010
Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the 2010 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2010
2009
Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.
IEEE Micro, 2009
IEEE J. Solid State Circuits, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Proceedings of the 2009 IEEE International Conference on Robotics and Automation, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Design-space exploration of backplane receivers with high-speed ADCs and digital equalization.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the 2009 International Conference on Compilers, 2009
2008
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability.
IEEE Micro, 2008
IEEE J. Solid State Circuits, 2008
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
J. Low Power Electron., 2008
A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Design of low-power short-distance opto-electronic transceiver front-ends with scalable supply voltages and frequencies.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A review of actuation and power electronics options for flapping-wing robotic insects.
Proceedings of the 2008 IEEE International Conference on Robotics and Automation, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 16th International Conference on Computer Communications and Networks, 2007
Proceedings of the Global Communications Conference, 2007
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), 2006
Adaptive-Bandwidth Mixing PLL/DLL Based Multi-Phase Clock Generator for Optimal Jitter Performance.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Phase Mismatch Detection and Compensation for PLL/DLL Based Multi-Phase Clock Generator.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations.
Proceedings of the 2006 International Conference on Compilers, 2006
2005
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005
2004
Pipelined parallel architecture for high throughput MAP detectors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Jitter in high-speed serial and parallel links.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A mixed PLL/DLL architecture for low jitter clock generation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE J. Solid State Circuits, 2003
2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
2000
IEEE J. Solid State Circuits, 2000
1999
IEEE J. Solid State Circuits, 1999
1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996