S. M. Aziz

According to our database, S. M. Aziz authored at least 4 papers between 1993 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits.

S. M. Aziz, Joarder Kamruzzaman

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1995

A C-testable modified Booth's array multiplier.

S. M. Aziz

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994

On Testability of Differential Split-Level CMOS Circuits.

S. M. Aziz, W. A. J. Waller

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic.

W. A. J. Waller, S. M. Aziz

Proceedings of the VLSI 93, 1993