S. Wayne Bollinger

According to our database, S. Wayne Bollinger authored at least 9 papers between 1988 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

Design planning for high-performance ASICs.

John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang

IBM J. Res. Dev., 1996

1994

Test generation for I_DDQ testing of bridging faults in CMOS circuits.

S. Wayne Bollinger, Scott F. Midkiff

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

Classification of bridging faults in CMOS circuits: experimental results and implications for test.

Scott F. Midkiff, S. Wayne Bollinger

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992

Hierarchical test generation for CMOS circuits.

S. Wayne Bollinger

PhD thesis, 1992

An investigation of circuit partitioning for parallel test generation.

S. Wayne Bollinger, Scott F. Midkiff

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

Heuristic Technique for Processor and Link Assignment in Multicomputers.

S. Wayne Bollinger, Scott F. Midkiff

IEEE Trans. Computers, 1991

Circuit-level classification and testability analysis for CMOS faults.

Scott F. Midkiff, S. Wayne Bollinger

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits.

S. Wayne Bollinger, Scott F. Midkiff

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1988

Processor and Link Assignment in Multicomputers Using Simulated Annealing.

S. Wayne Bollinger, Scott F. Midkiff

Proceedings of the International Conference on Parallel Processing, 1988