Vasant B. Rao

According to our database, Vasant B. Rao authored at least 21 papers between 1985 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Design methodology for the IBM POWER7 microprocessor.

Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Bühler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen D. Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez

IBM J. Res. Dev., 2011

2002

Aggressive crunching of extracted RC netlists.

Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

1996

Design planning for high-performance ASICs.

John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang

IBM J. Res. Dev., 1996

1995

Delay Analysis of the Distributed RC Line.

Vasant B. Rao

Proceedings of the 32st Conference on Design Automation, 1995

1994

A characterization of the smallest eigenvalue of a graph.

Madhav P. Desai, Vasant B. Rao

J. Graph Theory, 1994

1993

On the Convergence of Reversible Markov Chains.

Madhav P. Desai, Vasant B. Rao

SIAM J. Matrix Anal. Appl., October, 1993

Constructive Heuristics and Lower Bounds for Graph Partitioning Based on a Principal-Components Approximation.

K. S. Arun, Vasant B. Rao

SIAM J. Matrix Anal. Appl., October, 1993

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1991

Combinatorial optimization by stochastic evolution.

Youssef Saab, Vasant B. Rao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Consistency checking and optimization of macromodels.

Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Convex Optimization Approach to Transistor Sizing for CMOS Circuits.

Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Rank reduction in graph partitioning.

K. S. Arun, Vasant B. Rao

Proceedings of the 1991 International Conference on Acoustics, 1991

1990

Fast effective heuristics for the graph bisectioning problem.

Youssef Saab, Vasant B. Rao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems.

Youssef Saab, Vasant B. Rao

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

A Stochastic Algorithm for Circuit Bi-Partitioning.

Youssef Saab, Vasant B. Rao

Proceedings of the Computing in the 90's, 1989

An Evolution-Based Approach to Partitioning ASIC Systems.

Youssef Saab, Vasant B. Rao

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Multi-Input Fuzzy Inference Engine on a Systolic Array.

MahmMahmoud A. Manzoul, Vasant B. Rao

Proceedings of the First International Conference on Industrial & Engineering Applications of Artificial Intelligence & Expert Systems, 1988

Partitioning issues in circuit simulation on multiprocessors.

David C. Yeh, Vasant B. Rao

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

Network Partitioning and Ordering for MOS VLSI Circuits.

Vasant B. Rao, Timothy N. Trick

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

HPEX: A Hierarchical Parasitic Circuit Extractor.

Shun-Lin Su, Vasant B. Rao, Timothy N. Trick

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1985

Switch-Level Timing Simulation of MOS VLSI Circuits

Vasant B. Rao

PhD thesis, 1985