Sandeep Mishra

According to our database1, Sandeep Mishra authored at least 16 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.



In proceedings 
PhD thesis 





Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
J. Inf. Sci. Eng., 2020

Low-power content addressable memory design using two-layer P-N match-line control and sensing.
Integr., 2020

The analogy of matchline sensing techniques for content addressable memory (CAM).
IET Comput. Digit. Tech., 2020

RecSal : Deep Recursive Supervision for Visual Saliency Prediction.
CoRR, 2020

Comparing coherence measures for <i>X</i> states: Can quantum states be ordered based on quantum coherence?
Quantum Inf. Process., 2019

Low discharge precharge free matchline structure for energy-efficient search using CAM.
Integr., 2019

A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

Detection and Imaging of Moving Targets With LiMIT SAR Data.
IEEE Trans. Geosci. Remote. Sens., 2018

Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory.
IEEE Trans. Consumer Electron., 2018

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Self-Controlled High-Performance Precharge-Free Content-Addressable Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016