Jyotishman Saikia

According to our database, Jyotishman Saikia authored at least 10 papers between 2017 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.

Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-Sun Seo, Mingoo Seok

IEEE J. Solid State Circuits, May, 2023

A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.

Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-Sun Seo

IEEE J. Solid State Circuits, 2023

FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.

Jyotishman Saikia, Amitesh Sridharan, Injune Yeo, Shreyas K. Venkataramanaiah, Deliang Fan, Jae-Sun Seo

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.

Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.

Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.

Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design.

Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.

Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme.

Sandeep Mishra, Telajala Venkata Mahendra, Jyotishman Saikia, Anup Dandapat

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.

Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017