Billy Koo

According to our database, Billy Koo authored at least 7 papers between 2018 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

37.3 A 2nm All-Digital 14.4Gb/s/pin LPDDR6 PHY with Quarter-Rate Clocking Architecture and Multi-Level FIFO-Based Speculative DFE.

Yoonjae Choi, Daero Kim, Myunggon Kim, Sangmin Lee, Hansol Kang, Gwangwon Lee, Yoonhyung Kim, Sungsik Kang, Hyun Cho, Boyoung Kang, Kyoungwon Lee, Jaegeun Song, Jinho Choi, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Hyo-Gyuem Rhew

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025

TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface.

Hari Vijay Venkatanarayanan, Rustum Prasad Sahu, Maheswara Alamuru, Ergam Reddy Battini, Syed Mohammed Haroon, Saurav Suman, Deepika Mallela, Sanjeeb Kumar Ghosh, Billy Koo

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.

Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo Gyuem Rhew, Jongshin Shin

IEEE J. Solid State Circuits, January, 2024

A 4-nm 9.6-Gb/s/pin LPDDR5X PHY With Adaptive Driver Strength Control and Fast Periodic Training for Full DVFS DRAM.

Yoonjae Choi, Jaegeun Song, Daero Kim, Myunggon Kim, Jiyeon Park, Jinho Choi, Changki Kwon, Minho Seo, Jihun Oh, Shinyoung Yi, Billy Koo, Kwanyeob Chae, Jongshin Shin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.

Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2019

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.

Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.

Kwanyeob Chae, Billy Koo, Jihun Oh, Sanghune Park, Jongshin Shin, Jaehong Park

Proceedings of the International SoC Design Conference, 2018