Santanu Sarkar
Orcid: 0000-0002-9284-5654Affiliations:
- Indian Institute of Technology, Kharagpur, India
According to our database1,
Santanu Sarkar
authored at least 9 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
A Low-Power 10-bit SAR ADC with an Integrated CDAC and C-MOSCAP DAC for Implantable Pacemakers.
Proceedings of the 28th International Symposium on VLSI Design and Test, 2024
A 13-Bit Resolution High Performance Time Domain Comparator Using Intermediate Buffer Based VCO.
Proceedings of the IEEE Region 10 Conference, 2024
An 8-bit 1 MS/s Low-Power SAR ADC with an Enhanced EPC for Implantable Medical Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2022
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2015
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters.
Microelectron. J., 2014
2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
2008
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2006
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006