Arindrajit Ghosh

According to our database, Arindrajit Ghosh authored at least 5 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Compiler compatible 5.66 Mb/mm² 8T 1R1W register file in 14 nm FinFET technology.

Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee

Integr., 2020

2018

Contention free delayed keeper for high density large signal sensing memory compiler.

Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee

Integr., 2018

2006

A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology.

Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A 160MSPS 8-Bit Pipeline Based ADC.

Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm² Segmented Current Steering CMOS DAC.

Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005