Santosh Yachareni

According to our database, Santosh Yachareni authored at least 6 papers between 2020 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

High speed low power SEU tolerant Pseudo dual port memory in 7nm.

Suresh Babu Kotha, Kumar Rahul, Mohammad Anees, Santosh Yachareni, Subodh Kumar

Proceedings of the International Symposium on Networks, Computers and Communications, 2021

Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA.

Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni

Proceedings of the International Symposium on Networks, Computers and Communications, 2021

Robust Adaptive Read Scheme for 7nm Configuration SRAMs.

Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Narendra Kumar Pulipati, Joy Chen, Teja Masina

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Mitigation of the impact of across chip systematic process variation using a novel system level design.

Nabanita Ghoshal, Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Area and power efficient ECC for multiple adjacent bit errors in SRAMs.

Kumar Rahul, Santosh Yachareni

Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Deterministic Algorithm to generate SEC-DED-DAEC H-Matrix for SRAMs in FPGAs for reliable space applications.

Kumar Rahul, Santosh Yachareni

Proceedings of the 5th International Conference on Computing, Communication and Security, 2020