Santosh Yachareni

According to our database1, Santosh Yachareni authored at least 8 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Low-Supply, Sub-mW 1 GHz Ring Oscillator Achieving < 5% Frequency Variation Across PVT for Reliable On-Chip Clocking.
Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025
A bidirectional frequency detector independent of input transition density for a wide-tuning range applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2021
High speed low power SEU tolerant Pseudo dual port memory in 7nm.
Proceedings of the International Symposium on Networks, Computers and Communications, 2021

Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA.
Proceedings of the International Symposium on Networks, Computers and Communications, 2021

Robust Adaptive Read Scheme for 7nm Configuration SRAMs.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Mitigation of the impact of across chip systematic process variation using a novel system level design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
Area and power efficient ECC for multiple adjacent bit errors in SRAMs.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Deterministic Algorithm to generate SEC-DED-DAEC H-Matrix for SRAMs in FPGAs for reliable space applications.
Proceedings of the 5th International Conference on Computing, Communication and Security, 2020


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