Satoru Isomura

According to our database, Satoru Isomura authored at least 2 papers between 1996 and 2000.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2000

Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond.

Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1996

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.

Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta

IEEE J. Solid State Circuits, 1996